Mottaqiallah Taouil

Orcid: 0000-0002-9911-4846

According to our database1, Mottaqiallah Taouil authored at least 139 papers between 2010 and 2024.

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Bibliography

2024
Survey on Architectural Attacks: A Unified Classification and Attack Model.
ACM Comput. Surv., February, 2024

2023
A Survey on Machine Learning in Hardware Security.
ACM J. Emerg. Technol. Comput. Syst., April, 2023

Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Device-Aware Test for Ion Depletion Defects in RRAMs.
Proceedings of the IEEE International Test Conference, 2023

Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs.
Proceedings of the IEEE European Test Symposium, 2023

Dependability of Future Edge-AI Processors: Pandora's Box.
Proceedings of the IEEE European Test Symposium, 2023

Online Fault Detection and Diagnosis in RRAM.
Proceedings of the IEEE European Test Symposium, 2023

Memristor-Based Lightweight Encryption.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

A Pre-Silicon Power Leakage Assessment Based on Generative Adversarial Networks.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

Device-Aware Test for Back-Hopping Defects in STT-MRAMs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Characterization and Test of Intermittent Over RESET in RRAMs.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Device Aware Diagnosis for Unique Defects in STT-MRAMs.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
Instruction flow-based detectors against fault injection attacks.
Microprocess. Microsystems, October, 2022

APmap: An Open-Source Compiler for Automata Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs.
IEEE Trans. Computers, 2022

A Survey on Memory-centric Computer Architectures.
ACM J. Emerg. Technol. Comput. Syst., 2022

Defects, Fault Modeling, and Test Development Framework for RRAMs.
ACM J. Emerg. Technol. Comput. Syst., 2022

Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning.
IEEE Access, 2022

On BTI Aging Rejuvenation in Memory Address Decoders.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

Structured Test Development Approach for Computation-in-Memory Architectures.
Proceedings of the IEEE International Test Conference in Asia, 2022

Hierarchical Memory Diagnosis.
Proceedings of the IEEE European Test Symposium, 2022

Smart Redundancy Schemes for ANNs Against Fault Attacks.
Proceedings of the IEEE European Test Symposium, 2022

PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory.
Proceedings of the IEEE European Test Symposium, 2022

Exploiting PUF Variation to Detect Fault Injection Attacks.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

Reliability Analysis of FinFET-Based SRAM PUFs for 16nm, 14nm, and 7nm Technology Nodes.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Using Hopfield Networks to Correct Instruction Faults.
Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021
Hard-to-Detect Fault Analysis in FinFET SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Applying Thermal Side-Channel Attacks on Asymmetric Cryptography.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Defect and Fault Modeling Framework for STT-MRAM Testing.
IEEE Trans. Emerg. Top. Comput., 2021

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects.
J. Electron. Test., 2021

Multi-Bit Blinding: A Countermeasure for RSA Against Side Channel Attacks.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Deterministic and Statistical Strategies to Protect ANNs against Fault Injection Attacks.
Proceedings of the 18th International Conference on Privacy, Security and Trust, 2021

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions.
Proceedings of the IEEE International Test Conference, 2021

LightRoAD: Lightweight Rowhammer Attack Detector.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs.
Proceedings of the 26th IEEE European Test Symposium, 2021

Intermittent Undefined State Fault in RRAMs.
Proceedings of the 26th IEEE European Test Symposium, 2021

Power Side Channel Attacks: Where Are We Standing?
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Improving the Detection of Undefined State Faults in FinFET SRAMs.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Impact of Data Pre-Processing Techniques on Deep Learning Based Power Attacks.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Protecting IoT Devices through a Hardware-driven Memory Verification.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Revealing the Secrets of Spiking Neural Networks: The Case of Izhikevich Neuron.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

GRINCH: A Cache Attack against GIFT Lightweight Cipher.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures.
IEEE Trans. Emerg. Top. Comput., 2020

A Classification of Memory-Centric Computing.
ACM J. Emerg. Technol. Comput. Syst., 2020

Public-Key Based Authentication Architecture for IoT Devices Using PUF.
CoRR, 2020

Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests.
CoRR, 2020

An Energy-Efficient Current-Controlled Write and Read Scheme for Resistive RAMs (RRAMs).
IEEE Access, 2020

S-NET: A Confusion Based Countermeasure Against Power Attacks for SBOX.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects.
Proceedings of the IEEE Latin-American Test Symposium, 2020

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs.
Proceedings of the IEEE International Test Conference, 2020

Guard-NoC: A Protection Against Side-Channel Attacks for MPSoCs.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

RNN-Based Detection of Fault Attacks on RSA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Device-Aware Test for Emerging Memories: Enabling Your Test Program for DPPB Level.
Proceedings of the IEEE European Test Symposium, 2020

LiD-CAT: A Lightweight Detector for Cache ATtacks.
Proceedings of the IEEE European Test Symposium, 2020

Modeling Static Noise Margin for FinFET based SRAM PUFs.
Proceedings of the IEEE European Test Symposium, 2020

G-PUF: An Intrinsic PUF Based on GPU Error Signatures.
Proceedings of the IEEE European Test Symposium, 2020

Testing Scouting Logic-Based Computation-in-Memory Architectures.
Proceedings of the IEEE European Test Symposium, 2020

eSRAM Reliability: Why is it still not optimally solved?
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

A Security Verification Template to Assess Cache Architecture Vulnerabilities.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

Impact of Magnetic Coupling and Density on STT-MRAM Performance.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Mitigation of Sense Amplifier Degradation Using Skewed Design.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

The Power of Computation-in-Memory Based on Memristive Devices.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Challenges and Solutions in Emerging Memory Testing.
IEEE Trans. Emerg. Top. Comput., 2019

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation.
J. Low Power Electron., 2019

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era.
IEEE Access, 2019

Enhanced Scouting Logic: A Robust Memristive Logic Design Scheme.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

A computation-in-memory accelerator based on resistive devices.
Proceedings of the International Symposium on Memory Systems, 2019

Software-Based Mitigation for Memory Address Decoder Aging.
Proceedings of the IEEE Latin American Test Symposium, 2019

Testing Computation-in-Memory Architectures Based on Emerging Memories.
Proceedings of the IEEE International Test Conference, 2019

Device-Aware Test: A New Test Approach Towards DPPB Level.
Proceedings of the IEEE International Test Conference, 2019

Reliability Modeling and Mitigation for Embedded Memories.
Proceedings of the IEEE International Test Conference, 2019

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing.
Proceedings of the 24th IEEE European Test Symposium, 2019

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs.
Proceedings of the 24th IEEE European Test Symposium, 2019

Hardware-Based Aging Mitigation Scheme for Memory Address Decoder.
Proceedings of the 24th IEEE European Test Symposium, 2019

Time-division Multiplexing Automata Processor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Methodology for Application-Dependent Degradation Analysis of Memory Timing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Applications of Computation-In-Memory Architectures based on Memristive Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Memory and Communication Profiling for Accelerator-Based Platforms.
IEEE Trans. Computers, 2018

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs.
Microelectron. Reliab., 2018

Impact and mitigation of SRAM read path aging.
Microelectron. Reliab., 2018

Ionizing radiation modeling in DRAM transistors.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Electrical Modeling of STT-MRAM Defects.
Proceedings of the IEEE International Test Conference, 2018

Testing Resistive Memories: Where are We and What is Missing?
Proceedings of the IEEE International Test Conference, 2018

Device aging: A reliability and security concern.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Memristive devices for computation-in-memory.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Degradation analysis of high performance 14nm FinFET SRAM.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
On the Implementation of Computation-in-Memory Parallel Adder.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Memristive devices for computing: Beyond CMOS and beyond von Neumann.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Interconnect networks for resistive computing architectures.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

On the robustness of memristor based logic gates.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

Mitigation of sense amplifier degradation using input switching.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Synthesizing HDL to memristor technology: A generic framework.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Parallel matrix multiplication on memristor-based computation-in-memory architecture.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Non-volatile look-up table based FPGA implementations.
Proceedings of the 11th International Design & Test Symposium, 2016

Read path degradation analysis in SRAM.
Proceedings of the 21th IEEE European Test Symposium, 2016

Boolean logic gate exploration for memristor crossbar.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Comparative BTI analysis for various sense amplifier designs.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching.
ACM Trans. Design Autom. Electr. Syst., 2015

Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Testing Open Defects in Memristor-Based Memories.
IEEE Trans. Computers, 2015

Integral impact of BTI and voltage temperature variation on SRAM sense amplifier.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Interconnect networks for memristor crossbar.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Computation-in-memory based parallel adder.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Memory profiling for intra-application data-communication quantification: A survey.
Proceedings of the 10th International Design & Test Symposium, 2015

BTI analysis of SRAM write driver.
Proceedings of the 10th International Design & Test Symposium, 2015

Fast boolean logic mapped on memristor crossbar.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

On resistive open defect detection in DRAMs: The charge accumulation effect.
Proceedings of the 20th IEEE European Test Symposium, 2015

Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Memristor based computation-in-memory architecture for data-intensive applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Yield and Cost Analysis or 3D Stacked ICs.
PhD thesis, 2014

Quality versus cost analysis for 3D Stacked ICs.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface.
Proceedings of the 2014 International Test Conference, 2014

Interconnect test for 3D stacked memory-on-logic.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Exploring test opportunities for memory and interconnects in 3D ICs.
Proceedings of the 8th International Design and Test Symposium, 2013

Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity.
Proceedings of the 8th International Design and Test Symposium, 2013

Impact of mid-bond testing in 3D stacked ICs.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Is TSV-based 3D integration suitable for inter-die memory repair?
Proceedings of the Design, Automation and Test in Europe, 2013

Using 3D-COSTAR for 2.5D test cost optimization.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost.
J. Electron. Test., 2012

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories.
J. Electron. Test., 2012

On optimizing test cost for Wafer-to-Wafer 3D-stacked ICs.
Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

2011
On modeling and optimizing cost in 3D Stacked-ICs.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories.
Proceedings of the 16th European Test Symposium, 2011

Stacking order impact on overall 3D die-to-wafer Stacked-IC cost.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Yield Improvement and Test Cost Optimization for 3D Stacked ICs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs.
Proceedings of the 2011 IEEE International Test Conference, 2010

Performance and bandwidth optimization for biological sequence alignment.
Proceedings of the 5th International Design and Test Workshop, 2010

Test Cost Analysis for 3D Die-to-Wafer Stacking.
Proceedings of the 19th IEEE Asian Test Symposium, 2010


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