Lounis Kessal

According to our database, Lounis Kessal authored at least 24 papers between 1995 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Implementation of a Bio-Inspired Neural Architecture for Autonomous Vehicles on a Multi-FPGA Platform.

Tarek Elouaret, Sylvain Colomer, Frédéric de Melo, Nicolas Cuperlier, Olivier Romain, Lounis Kessal, Stéphane Zuckerman

Sensors, 2023

2022

Implementation of a bio-inspired neural architecture for autonomous vehicle on a reconfigurable platform.

Tarek Elouaret, Sylvain Colomer, Frédéric Demelo, Nicolas Cuperlier, Olivier Romain, Lounis Kessal, Stéphane Zuckerman

Proceedings of the 31st IEEE International Symposium on Industrial Electronics, 2022

2019

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes.

Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Emmanuel Boutillon, Chris Winstead, Bane Vasic

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Position Paper: Prototyping Autonomous Vehicles Applications with Heterogeneous Multi-FpgaSystems.

Tarek Elouaret, Stéphane Zuckerman, Lounis Kessal, Yoan Espada, Nicolas Cuperlier, Guillaume Bresson, Fethi Ben Ouezdou, Olivier Romain

Proceedings of the UK/China Emerging Technologies, 2019

2018

Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes.

Khoa Le, David Declercq, Fakhreddine Ghaffari, Lounis Kessal, Oana Boncalo, Valentin Savin

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes.

Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Valentin Savin, Oana Boncalo

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Density evolution thresholds for noise-against-noise min-sum decoders.

Franklin Cochachin, David Declercq, Emmanuel Boutillon, Lounis Kessal

Proceedings of the 28th IEEE Annual International Symposium on Personal, 2017

2014

FPGA-implementation of a bio-inspired medical hearing aid based DWT-OLA.

Lotfi Bendaouia, Hassen Salhi, Si Mahmoud Karabernou, Lounis Kessal, Fayçal Ykhlef

Proceedings of the International Conference on Audio, 2014

2012

Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications.

Laurent Gantel, Amel Khiar, Benoît Miramond, Mohamed El Amine Benkhelifa, Lounis Kessal, Fabrice Lemonnier, Jimmy Le Rhun

ACM Trans. Reconfigurable Technol. Syst., 2012

2011

Dataflow programming model for reconfigurable computing.

Laurent Gantel, Amel Khiar, Benoît Miramond, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, Lounis Kessal

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

2009

Hardware Architecture for Pattern Recognition in Gamma-Ray Experiment.

Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal

EURASIP J. Embed. Syst., 2009

2008

Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing.

Lounis Kessal, Nicolas Abel, Si Mahmoud Karabernou, Didier Demigny

J. Real Time Image Process., 2008

Neural network hardware architecture for pattern recognition in the HESS2 project.

Narayanan Ramanan, Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal

Proceedings of the 16th European Symposium on Artificial Neural Networks, 2008

2007

Erratum to "Real-time FPGA implementation of Hough Transform using gradient and CORDIC algorithm" [Image and Vision Computing 23 (2005) 1009-1017].

Si Mahmoud Karabernou, Lounis Kessal, Fayçal Terranti

Image Vis. Comput., 2007

2006

Clear Stream towards Dynamically Reconfigurable Systems on Chip.

Nicolas Abel, Lounis Kessal, Sébastien Pillement, Didier Demigny

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

2004

Design flexibility using fpga dynamical reconfiguration.

Nicolas Abel, Lounis Kessal, Didier Demigny

Proceedings of the 2004 International Conference on Image Processing, 2004

2003

Real-time image processing with dynamically reconfigurable architecture.

Lounis Kessal, Nicolas Abel, Didier Demigny

Real Time Imaging, 2003

2001

Two ASIC for Low and Middle Levels of Real Time Image Processing.

P. Lamaty, B. Mazar, Didier Demigny, Lounis Kessal, Si Mahmoud Karabernou

Proceedings of the SOC Design Methodologies, 2001

Reconfigurable Architecture Using High Speed FPGA.

Lounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, Si Mahmoud Karabernou

Proceedings of the SOC Design Methodologies, 2001

Fast Recursive Implementation of the Gaussian Filter.

Didier Demigny, Lounis Kessal, J. Pons

Proceedings of the SOC Design Methodologies, 2001

2000

Reconfigurable Hardware for Real Time Image Processing.

Lounis Kessal, Didier Demigny, N. Boudouani, R. Bourguiba

Proceedings of the 2000 International Conference on Image Processing, 2000

How to Use High Speed Reconfigurable FPGA for Real Time Image Processing?

Didier Demigny, Lounis Kessal, R. Bourguiba, N. Boudouani

Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000

1997

Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection.

F. G. Lorca, Lounis Kessal, Didier Demigny

Proceedings of the Proceedings 1997 International Conference on Image Processing, 1997

1995

Evaluation of edge detectors performances with a discrete expression of Canny's criteria.

Didier Demigny, F. G. Lorca, Lounis Kessal

Proceedings of the Proceedings 1995 International Conference on Image Processing, 1995