Pak Shing Chau

According to our database, Pak Shing Chau authored at least 4 papers between 1996 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface.

Masum Hossain, Farrukh Aquil, Pak Shing Chau, Brian Tsang, Phuong Le, Jason Wei, Teva Stone, Barry Daly, Chanh Tran, John C. Eble, Kurt Knorpp, Jared Zerbe

IEEE J. Solid State Circuits, 2014

2001

1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus.

Jared L. Zerbe, Pak Shing Chau, Carl W. Werner, Timothy P. Thrush, H. J. Liaw, Bruno W. Garlepp, Kevin S. Donnelly

IEEE J. Solid State Circuits, 2001

1999

A portable digital DLL for high-speed CMOS interface circuits.

Bruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak Shing Chau, Jared L. Zerbe, Charlie Huang, Chanh Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, Mark A. Horowitz

IEEE J. Solid State Circuits, 1999

1996

A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC.

Kevin S. Donnelly, Yiu-Fai Chan, John T. C. Ho, Chanh Tran, Samir Patel, Benedict Lau, Jun Kim, Pak Shing Chau, Charlie Huang, Jason Wei, Leung Yu, Richard Tarver, Rakhee Kulkarni, Don Stark, Mark Johnson

IEEE J. Solid State Circuits, 1996