Masum Hossain

According to our database1, Masum Hossain authored at least 34 papers between 2006 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture.
IEEE J. Solid State Circuits, 2021

2020
Sequence-Coded Multilevel Signaling for High-Speed Interface.
IEEE J. Solid State Circuits, 2020


6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
DDJ-Adaptive SAR TDC-Based Timing Recovery for Multilevel Signaling.
IEEE J. Solid State Circuits, 2019

Broadband-Tunable Cascaded Vernier Silicon Photonic Microring Filter with Temperature Tracking.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

Affordable Sequence Decoding Techniques for High Speed SerDes.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 32Gb/s 2.9pJ/b Transceiver for Sequence-Coded PAM-4 Signalling with 4-to-6dB SNR Gain in 28nm FDSOI CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 100-MS/s-5-GS/s, 13-5-bit Nyquist-Rate Reconfigurable Time-Domain ADC.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Analog to Sequence Converter-Based PAM-4 Receiver With Built-In Error Correction.
IEEE J. Solid State Circuits, 2018

Channel-Adaptive ADC and TDC for 28 Gb/s PAM-4 Digital Receiver.
IEEE J. Solid State Circuits, 2018

Investigation of Wideband Substrate-Integrated Vertically-Polarized Electric Dipole Antenna and Arrays for mm-Wave 5G Mobile Devices.
IEEE Access, 2018

A Bimodal (NRZ/PAM-4) ISI Tolerant Timing Recovery with Adaptive DDJ Equalization.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
Time-Domain Arithmetic Logic Unit With Built-In Interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter.
IEEE J. Solid State Circuits, 2017

High speed ADCs for wireline applications.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Channel adaptive ADC and TDC for 28 Gb/s PAM-4 digital receiver.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28nm FDSOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

A 79dB SNDR, 10MHz BW, 675MS/s open-loop time-based ADC employing a 1.15ps SAR-TDC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

2014
A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface.
IEEE J. Solid State Circuits, 2014

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014

2012
A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
A Low Power Frequency Synthesizer for 60-GHz Wireless Personal Area Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS.
IEEE J. Solid State Circuits, 2011

2010
Multi-Gb/s Bit-by-Bit Receiver Architectures for 1-D Partial-Response Channels.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

5-10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS.
IEEE J. Solid State Circuits, 2010

A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
CMOS Oscillators for Clock Distribution and Injection-Locked Deskew.
IEEE J. Solid State Circuits, 2009

2008
20 GHz low power QVCO and De-skew techniques in 0.13μm digital CMOS.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2006
A 19-GHz Broadband Amplifier Using a g<sub>m</sub>-Boosted Cascode in 0.18-μm CMOS.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006


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