Carl W. Werner

According to our database1, Carl W. Werner authored at least 8 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Differential Edge Modulation Signaling for Low-Energy, High-Speed Wireline Communication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

2011
A Multiband Transceiver System in 45-nm CMOS for Extended Data Rate through Notchy Wireline Channels.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

2010
Low-skew clock distribution using zero-phase-clock-buffer DLLs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2007
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery.
IEEE J. Solid State Circuits, 2005

Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell.
IEEE J. Solid State Circuits, 2003

2001
1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus.
IEEE J. Solid State Circuits, 2001


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