Phuong Le

According to our database1, Phuong Le authored at least 7 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Unveiling Comparative Sentiments in Vietnamese Product Reviews: A Sequential Classification Framework.
CoRR, 2024

2014
A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface.
IEEE J. Solid State Circuits, 2014

2013
A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver.
IEEE J. Solid State Circuits, 2013

2012
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.
IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.
IEEE J. Solid State Circuits, 2012

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011


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