Parthasarathy M. B. Rao

According to our database, Parthasarathy M. B. Rao authored at least 3 papers between 2013 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames.

Mojtaba Ebrahimi, Parthasarathy Murali B. Rao, Razi Seyyedi, Mehdi Baradaran Tahoori

IEEE Trans. Very Large Scale Integr. Syst., 2016

2014

Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes.

Parthasarathy M. B. Rao, Mojtaba Ebrahimi, Razi Seyyedi, Mehdi Baradaran Tahoori

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Altering LUT configuration for wear-out mitigation of FPGA-mapped designs.

Parthasarathy M. B. Rao, Abdulazim Amouri, Saman Kiamehr, Mehdi Baradaran Tahoori

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013