Saman Kiamehr

According to our database1, Saman Kiamehr authored at least 53 papers between 2011 and 2020.

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Bibliography

2020
Achieving Energy Efficiency for Near-Threshold Circuits Through Postfabrication Calibration and Adaptation.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Selective Flip-Flop Optimization for Reliable Digital Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2018
An Experimental Evaluation and Analysis of Transient Voltage Fluctuations in FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Reliable memory PUF design for low-power applications.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Balancing resiliency and energy efficiency of functional units in ultra-low power systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods.
Integr., 2017

Post-fabrication calibration of Near-Threshold circuits for energy efficiency.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Aging-aware coding scheme for memory arrays.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Leveraging aging effect to improve SRAM-based true random number generators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Error Propagation Aware Timing Relaxation For Approximate Near Threshold Computing.
Proceedings of the 54th Annual Design Automation Conference, 2017

Workload-aware static aging monitoring of timing-critical flip-flops.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Hold-time violation analysis and fixing in near-threshold region.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A cross-layer approach for resiliency and energy efficiency in near threshold computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Temperature-aware Dynamic Voltage Scaling for Near-Threshold Computing.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Analysis of transient voltage fluctuations in FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Variation-aware near threshold circuit synthesis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Area-energy tradeoffs of logic wear-leveling for BTI-induced aging.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach.
PhD thesis, 2015

Extending standard cell library for aging mitigation.
IET Comput. Digit. Tech., 2015

Analysis and optimization of flip-flops under process and runtime variations.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Cross-layer resilient system design flow.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Aging guardband reduction through selective flip-flop optimization.
Proceedings of the 20th IEEE European Test Symposium, 2015

On-line prediction of NBTI-induced aging rates.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Aging mitigation in memory arrays using self-controlled bit-flipping technique.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Physical design of CNTFET-based circuits for yield improvement.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Aging effects in FPGAs: an experimental analysis.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Aging-aware standard cell library design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Adaptive Mitigation of Parameter Variations.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Negative Bias Temperature Instability-Aware Instruction Scheduling: A Cross-Layer Approach.
J. Low Power Electron., 2013

Chip-level modeling and analysis of electrical masking of soft errors.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Aging-aware timing analysis considering combined effects of NBTI and PBTI.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Aging-aware logic synthesis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Altering LUT configuration for wear-out mitigation of FPGA-mapped designs.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing.
Proceedings of the 18th IEEE European Test Symposium, 2013

Instruction-set extension under process variation and aging effects.
Proceedings of the Design, Automation and Test in Europe, 2013

Incorporating the impacts of workload-dependent runtime variations into timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2013

Statistical analysis of BTI in the presence of process-induced voltage and temperature variations.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Investigation of aging effects in different implementations and structures of programmable routing resources of FPGAs.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

NBTI mitigation by optimized NOP assignment and insertion.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Modeling and estimation of power supply noise using linear programming.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A linear programming approach for minimum NBTI vector selection.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Investigation of NBTI and PBTI induced aging in different LUT implementations.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011


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