Razi Seyyedi

According to our database, Razi Seyyedi authored at least 12 papers between 2013 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Globally Accurate Locally Inaccurate (GALI): On the Combination of Time-Triggered Architectures with Instruction Accurate Simulators for the Analysis of System Behavior.

Razi Seyyedi

PhD thesis, 2023

2020

Functional test environment for time-triggered control systems in complex MPSoCs.

Razi Seyyedi, Sören Schreiner, Maher Fakih, Kim Grüttner, Wolfgang Nebel

Microprocess. Microsystems, 2020

2018

Towards power management verification of time-triggered systems using virtual platforms.

Sören Schreiner, Razi Seyyedi, Maher Fakih, Kim Grüttner, Wolfgang Nebel

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Functional Test Environment for Time-Triggered Control Systems in Complex MPSoCs Using GALI.

Razi Seyyedi, Sören Schreiner, Maher Fakih, Kim Grüttner, Wolfgang Nebel

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems.

Maher Fakih, Alina Lenz, Mikel Azkarate-askasua, Javier Coronel, Alfons Crespo, Simon Davidmann, Juan Carlos Diaz Garcia, Nera González Romero, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Roman Obermaisser, Adele Maleki, Johnny Öberg, Mohamed Tagelsir Mohammadat, Jon Pérez-Cerrolaza, Ingo Sander, Ingemar Söderquist

Microprocess. Microsystems, 2017

Towards virtual prototyping of synchronous real-time systems on noc-based MPSoCs.

Razi Seyyedi, Mohamed Tagelsir Mohammadat, Maher Fakih, Kim Grüttner, Johnny Öberg, Duncan Graham

Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

2016

Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames.

Mojtaba Ebrahimi, Parthasarathy Murali B. Rao, Razi Seyyedi, Mehdi Baradaran Tahoori

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor.

Mojtaba Ebrahimi, Adrian Evans, Mehdi Baradaran Tahoori, Enrico Costenaro, Dan Alexandrescu, Vikas Chandra, Razi Seyyedi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Event-driven transient error propagation: A scalable and accurate soft error rate estimation approach.

Mojtaba Ebrahimi, Razi Seyyedi, Liang Chen, Mehdi Baradaran Tahoori

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales.

Mojtaba Ebrahimi, Adrian Evans, Mehdi Baradaran Tahoori, Razi Seyyedi, Enrico Costenaro, Dan Alexandrescu

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes.

Parthasarathy M. B. Rao, Mojtaba Ebrahimi, Razi Seyyedi, Mehdi Baradaran Tahoori

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Modeling symmetrical independent gate FinFET using predictive technology model.

Mohammad Yousef Zarei, Reza Asadpour, Siamak Mohammadi, Ali Afzali-Kusha, Razi Seyyedi

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013