Mojtaba Ebrahimi

According to our database1, Mojtaba Ebrahimi authored at least 52 papers between 2011 and 2020.

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Bibliography

2020
Selective Flip-Flop Optimization for Reliable Digital Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2018
Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
Bias Temperature Instability Mitigation via Adaptive Cache Size Management.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Aging-aware coding scheme for memory arrays.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Opportunistic write for fast and reliable STT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Cross-layer Soft Error Analysis and Mitigation at Nanoscale Technologies.
PhD thesis, 2016

Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Self-Timed Read and Write Operations in STT-MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Reliability-Aware Resource Allocation and Binding in High-Level Synthesis.
ACM Trans. Design Autom. Electr. Syst., 2016

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing.
IEEE Trans. Multi Scale Comput. Syst., 2016

Layout-Based Modeling and Mitigation of Multiple Event Transients.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Online soft-error vulnerability estimation for memory arrays.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Revisiting software-based soft error mitigation techniques via accurate error generation and propagation models.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Temperature-aware Dynamic Voltage Scaling for Near-Threshold Computing.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

System-level reliability evaluation through cache-aware software-based fault injection.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Variation-aware near threshold circuit synthesis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Invited - Cross-layer approaches for soft error modeling and mitigation.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Fault injection acceleration by simultaneous injection of non-interacting faults.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Application-aware cross-layer reliability analysis and optimization.
it Inf. Technol., 2015

Extending standard cell library for aging mitigation.
IET Comput. Digit. Tech., 2015

Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control Paths.
J. Electron. Test., 2015

Stepped parity: A low-cost multiple bit upset detection technique.
Proceedings of the 2015 IEEE International Test Conference, 2015

Cross-layer resilient system design flow.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Improving reliability, performance, and energy efficiency of STT-MRAM with dynamic write latency.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Aging guardband reduction through selective flip-flop optimization.
Proceedings of the 20th IEEE European Test Symposium, 2015

Reliability-aware operation chaining in high level synthesis.
Proceedings of the 20th IEEE European Test Symposium, 2015

Protecting caches against multi-bit errors using embedded erasure coding.
Proceedings of the 20th IEEE European Test Symposium, 2015

Fault injection acceleration by architectural importance sampling.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

Aging mitigation in memory arrays using self-controlled bit-flipping technique.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Event-driven transient error propagation: A scalable and accurate soft error rate estimation approach.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A fast, flexible, and easy-to-develop FPGA-based fault injection technique.
Microelectron. Reliab., 2014

Towards Cross-layer Reliability Analysis of Transient and Permanent Faults.
CoRR, 2014

Read disturb fault detection in STT-MRAM.
Proceedings of the 2014 International Test Conference, 2014

Avoiding unnecessary write operations in STT-MRAM for low power implementation.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Quantitative evaluation of register vulnerabilities in RTL control paths.
Proceedings of the 19th IEEE European Test Symposium, 2014

Aging-aware standard cell library design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Architectural aspects in design and analysis of SOT-based memories.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013

CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis.
J. Electron. Test., 2013

Chip-level modeling and analysis of electrical masking of soft errors.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Aging-aware logic synthesis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A layout-based approach for multiple event transient analysis.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

CLASS: Combined logic and architectural soft error sensitivity analysis.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
SCFIT: A FPGA-based fault injection technique for SEU fault model.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications.
Proceedings of the Design, Automation and Test in Europe, 2011


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