Patrick Satarzadeh

According to our database1, Patrick Satarzadeh authored at least 9 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Digital Correction of Time Interleaved DAC Mismatches.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2012
A 20mW 61dB SNDR (60MHz BW) 1b 3<sup>rd</sup>-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques.
IEEE J. Solid State Circuits, 2011

2010
A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Equalizer design and performance trade-offs in ADC-based serial links.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Adaptive Semiblind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Digital Calibration of a Nonlinear S/H.
IEEE J. Sel. Top. Signal Process., 2009

2007
Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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