Christoph Scholl
Affiliations:- University of Freiburg, Department of Computer Science, Germany
- Saarland University, Department of Computer Science, Saarbrücken, Germany (PhD 1997)
According to our database1,
Christoph Scholl
authored at least 91 papers
between 1994 and 2023.
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Bibliography
2023
Everything You Always Wanted to Know About Generalization of Proof Obligations in PDR.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
2022
Theor. Comput. Sci., 2022
Proceedings of the 25th International Conference on Theory and Applications of Satisfiability Testing, 2022
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2022
Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization.
Proceedings of the 22nd Formal Methods in Computer-Aided Design, 2022
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Symbolic Computer Algebra and SAT Based Information Forwarding for Fully Automatic Divider Verification.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
J. Satisf. Boolean Model. Comput., 2019
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2019, 2019
Proceedings of the 2019 Formal Methods in Computer Aided Design, 2019
fbPDR: In-depth combination of forward and backward analysis in Property Directed Reachability.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
A PSPACE Subclass of Dependency Quantified Boolean Formulas and Its Effective Solving.
Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019
2018
Dependency Quantified Boolean Formulas: An Overview of Solution Methods and Applications - Extended Abstract.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2018, 2018
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the Advanced Logic Synthesis, 2018
2017
Verification of linear hybrid systems with large discrete state spaces using counterexample-guided abstraction refinement.
Sci. Comput. Program., 2017
Sequential Verification Using Reverse PDR.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017
2016
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016
Proceedings of the 4th International Workshop on Quantified Boolean Formulas (QBF 2016) co-located with 19th International Conference on Theory and Applications of Satisfiability Testing (SAT 2016), 2016
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016
Proceedings of the Automated Technology for Verification and Analysis, 2016
Task Variants with Different Scratchpad Memory Consumption in Multi-Task Environments.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016
2015
Sci. Comput. Program., 2015
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2015, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the Automated Technology for Verification and Analysis, 2015
2014
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014
Proceedings of the Hardware and Software: Verification and Testing, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
IEEE Trans. Computers, 2013
Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2013
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013
Equivalence Checking for Partial Implementations Revisited.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013
Equivalence checking of partial designs using dependency quantified Boolean formulae.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Exact and fully symbolic verification of linear hybrid automata with large discrete state spaces.
Sci. Comput. Program., 2012
Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012
Enhanced Integration of QBF Solving Techniques.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012
Fully Symbolic Model Checking for Incomplete Systems of Timed Automata.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012
2011
Fully Symbolic Model Checking for Timed Automata.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
Verifying Incomplete Networks of Timed Automata.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Computer Aided Verification - 23rd International Conference, 2011
2010
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010
SAT Modulo BDD -- A Combined Verification Approach for Incomplete Designs.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010
A probabilistic and energy-efficient scheduling approach for online application in real-time systems.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 47th Design Automation Conference, 2010
2009
Computing Optimized Representations for Non-convex Polyhedra by Detection and Removal of Redundant Linear Constraints.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2009
Using Implications for Optimizing State Set Representations of Linear Hybrid Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009
Symbolic CTL Model Checking for Incomplete Designs by Selecting Property-Specific Subsets of Local Component Assumptions.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Proceedings of the Aktuelle Anwendungen in Technik und Wirtschaft, 2008
Proceedings of the International Multiconference on Computer Science and Information Technology, 2008
2007
Counterexample Generation for Incomplete Designs.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007
Computation of minimal counterexamples by using black box techniques and symbolic methods.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 3rd European Conference on Mobile Robots, 2007
Exact State Set Representations in the Verification of Linear Hybrid Systems with Large Discrete State Space.
Proceedings of the Automated Technology for Verification and Analysis, 2007
Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006
Advanced Unbounded CTL Model Checking By Using AIGs, BDD Sweeping, and Quantifier Scheduling.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006
Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling.
Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006
Proceedings of the Automated Technology for Verification and Analysis, 2006
2004
Filter Based Diagnosis for Multiple Design Errors.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004
Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004
2002
On WLCDs and the Complexity of Word-Level Decision Diagrams-A Lower Bound for Division.
Formal Methods Syst. Des., 2002
Equivalence Checking in the Presence of Incompletely Specified Boxes.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
2001
Don't Care Minimization of BMDs: Complexity and Algorithms.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001
Checking Equivalence for Partial Implementations.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
The multiple variable order problem for binary decision diagrams: theory and practical application.
Proceedings of ASP-DAC 2001, 2001
Kluwer, ISBN: 978-0-7923-7585-2, 2001
2000
State Traversal guided by Hamming Distance Profiles.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Datenstrukturen und effiziente Algorithmen für die Logiksynthese kombinatorischer Schaltungen.
Teubner, ISBN: 978-3-519-02945-8, 1999
1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Proceedings of the 1998 Design, 1998
1997
PhD thesis, 1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Minimizing ROBDD sizes of incompletely specified Boolean functionsby exploiting strong symmetries.
Proceedings of the European Design and Test Conference, 1997
1995
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1994
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994