Martin Keim

Mehdi Baradaran Tahoori

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Affordable and Comprehensive Testing of 3-D Stacked Die Devices.

[BibT_eX]

[DOI]

IEEE Des. Test, 2022

MBIST-based Trim-Search Test Time Reduction for STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

IEEE P1687.1: Extending the Network Boundaries for Test.

[BibT_eX]

[DOI]

Hans Martin von Staudt

Bradford G. Van Treuren

Songlin Zuo

Proceedings of the IEEE International Test Conference, 2022

2021

Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces.

[BibT_eX]

[DOI]

Hans Martin von Staudt

Bradford G. Van Treuren

Michele Portolan

Proceedings of the 26th IEEE European Test Symposium, 2021

MBIST-supported Trim Adjustment to Compensate Thermal Behavior of MRAM.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE European Test Symposium, 2021

Convolutional Compaction-Based MRAM Fault Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE European Test Symposium, 2021

2020

MBIST Supported Multi Step Trim for Reliable eMRAM Sensing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

Fast Bring-Up of an AI SoC through IEEE 1687 Integrating Embedded TAPs and IEEE 1500 Interfaces.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

Modeling Novel Non-JTAG IEEE 1687-Like Architectures.

[BibT_eX]

[DOI]

Hans Martin von Staudt

M. Abdalwahab

Bradford G. Van Treuren

Proceedings of the IEEE International Test Conference, 2020

IJTAG Through a Two-Pin Chip Interface.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

MBIST Support for Reliable eMRAM Sensing.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

Linking Chip, Board, and System Test via Standards.

[BibT_eX]

[DOI]

Michele Portolan

Proceedings of the IEEE European Test Symposium, 2020

2018

Innovative practices on memory test practice.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Implementing Design-for-Test Within a Tile-Based Design Methodology - Challenges and Solutions.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2018

2017

Generalizing Access to Instrumentation Embedded in a Semiconductor Device.

[BibT_eX]

[DOI]

Al Crouch

Michael Laisne

Computer, 2017

Adapting an industrial memory BIST solution for testing CAMs.

[BibT_eX]

[DOI]

Proceedings of the International Test Conference in Asia, 2017

2015

A case study: Leverage IEEE 1687 based method to automate modeling, verification, and test access for embedded instruments in a server processor.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

2014

Cell-Aware Test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Quo Vadis DFT?

[BibT_eX]

Proceedings of the Aspekte der Technischen Informatik, 2014

2013

Thinking About Adopting IEEE P1687?

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

Industrial Application of IEEE P1687 for an Automotive Product.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Re-using chip level DFT at board level.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Erik Larsson

Proceedings of the 17th IEEE European Test Symposium, 2012

2008

Automatic Test Pattern Generation for Interconnect Open Defects.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

Silicon Evaluation of Static Alternative Fault Models.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement.

[BibT_eX]

[DOI]

Proceedings of the 12th European Test Symposium, 2007

Scan Diagnosis and Its Successful Industrial Applications.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

2006

A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

2004

Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Symbolic methods for testing digital circuits.

[BibT_eX]

[DOI]

PhD thesis, 2003

Polynomial Formal Verification of Multipliers.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2003

2002

Sequential n -Detection Criteria: Keep It Simple.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

2001

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2001

2000

A parameterizable fault simulator for bridging faults.

[BibT_eX]

[DOI]

Piet Engelke

Proceedings of the 5th European Test Workshop, 2000

1999

Hybrid Fault Simulation for Synchronous Sequential Circuits.

[BibT_eX]

[DOI]

Rolf Krieger

J. Electron. Test., 1999

A scalable BIST architecture for delay faults.

[BibT_eX]

[DOI]

Proceedings of the 4th European Test Workshop, 1999

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.

[BibT_eX]

[DOI]

Nicole Drechsler

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

1997

On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Fault Simulation in Sequential Multi-Valued Logic Networks.

[BibT_eX]

[DOI]

Rolf Drechsler

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions.

[BibT_eX]

[DOI]

Rolf Drechsler

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

1996

On the (non-)resetability of synchronous sequential circuits.

[BibT_eX]

[DOI]

Birgitta Stenner

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1995

Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy.

[BibT_eX]

[DOI]

Rolf Krieger

Proceedings of the 32st Conference on Design Automation, 1995

1994

A Hybrid Fault Simulator for Synchronous Sequential Circuits.

[BibT_eX]

[DOI]

Rolf Krieger