Penelope Faure

According to our database, Penelope Faure authored at least 8 papers between 1992 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2002

Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA.

Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

A Discussion on Test Pattern Generation for FPGA - Implemented Circuits.

Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian

J. Electron. Test., 2001

IS-FPGA : a new symmetric FPGA architecture with implicit scan.

Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits.

Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Analyzing the test generation problem for an application-oriented test of FPGAs.

Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian

Proceedings of the 5th European Test Workshop, 2000

TOF: a tool for test pattern generation optimization of an FPGA application oriented test.

Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1993

Object-oriented system development.

Dennis de Champeaux, Doug Lea, Penelope Faure

Addison-Wesley, ISBN: 978-0-201-56355-9, 1993

1992

The Process of Object-Oriented Design.

Dennis de Champeaux, Doug Lea, Penelope Faure

Proceedings of the Seventh Annual Conference on Object-Oriented Programming Systems, 1992