Jean-Michel Portal
Orcid: 0000-0002-6722-053XAffiliations:
- Aix-Marseille University (AMU), France
According to our database1,
Jean-Michel Portal
authored at least 140 papers
between 1997 and 2023.
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Bibliography
2023
Powering AI at the Edge: A Robust, Memristor-based Binarized Neural Network with Near-Memory Computing and Miniaturized Solar Cell.
CoRR, 2023
1S1R Sub-Threshold Operation in Crossbar Arrays for Neural Networks Hardware Implementation.
Proceedings of the 30th International Conference on Mixed Design of Integrated Circuits and System, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Voltage-Dependent Synaptic Plasticity (VDSP): Unsupervised probabilistic Hebbian plasticity rule based on neurons membrane potential.
CoRR, 2022
Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy.
Adv. Intell. Syst., 2022
Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing.
Proceedings of the IEEE International Memory Workshop, 2022
2021
Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation Per Synapse.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks.
CoRR, 2021
A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the IEEE International Memory Workshop, 2021
Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications.
CoRR, 2020
Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations.
IEEE Access, 2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays.
CoRR, 2019
In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks.
CoRR, 2019
IEEE Access, 2019
Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Dual Detection of Heating and Photocurrent attacks (DDHP) Sensor using Hybrid CMOS/STT-MRAM.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
An Ultra-Low Power and High Performance Single Ended Sense Amplifier for Low Voltage Flash Memories.
J. Low Power Electron., 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
A Power Efficient Regulated Charge Pump Based on Charge Sharing for Contactless Devices: An Alternative to Four-Phase Charge Pumps.
J. Low Power Electron., 2017
High voltage recycling scheme to improve power consumption of regulated charge pumps.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Power efficiency optimization of charge pumps in embedded low voltage NOR flash memory.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017
An Ultra-Low Power and High Speed Single Ended Sense Amplifier for Non-Volatile Memories.
Proceedings of the New Generation of CAS, 2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
2016
Microelectron. Reliab., 2016
J. Electron. Test., 2016
Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
2015
Improvement of MOSFET matching characterization with calibrated multiplexed test structure.
Microelectron. Reliab., 2015
Dynamic current reduction of CMOS digital circuits through design and process optimization.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
Layout optimizations to decrease internal power and area in digital CMOS standard cells.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015
Low cost built-in-tuning of on-chip passive filters for low-if double quadrature rf receiver.
Proceedings of the 16th Latin-American Test Symposium, 2015
Improvement of a detection chain based on a VCO concept for microelectronic reliability under natural radiative environment.
Proceedings of the 16th Latin-American Test Symposium, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distributed Comput., 2014
J. Parallel Distributed Comput., 2014
Low Power Radio Frequency Transceiver with Built-In-Tuning of the Local Oscillator for Open Loop Modulation.
J. Low Power Electron., 2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the 15th Latin American Test Workshop, 2014
An innovative standard cells remapping method for in-circuit critical parameters monitoring.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Printed complementary organic thin film transistors based decoder for ferroelectric memory.
Proceedings of the ESSCIRC 2014, 2014
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Microelectron. Reliab., 2013
On the investigation of built-in tuning of RF receivers using on-chip polyphase filters.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Built-in tuning of the local oscillator for open loop modulation of low cost, low power RF transceiver.
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the 14th Latin American Test Workshop, 2013
A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 8th International Design and Test Symposium, 2013
A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
2012
J. Low Power Electron., 2012
Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability.
J. Low Power Electron., 2012
J. Electron. Test., 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
A new adustable Schmitt Trigger based on Dual Control Gate-Floating Gate Transistor (DCG-FGT).
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the International Symposium on Communications and Information Technologies, 2012
2011
Microelectron. Reliab., 2011
Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress.
Microelectron. Reliab., 2011
Using OxRRAM memories for improving communications of reconfigurable FPGA architectures.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Design challenges for prototypical and emerging memory concepts relying on resistance switching.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2009
Definition of an innovative filling structure for digital blocks : the DFM filler cell.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections.
Proceedings of the 14th IEEE European Test Symposium, 2009
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
2008
J. Low Power Electron., 2008
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
J. Electron. Test., 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 2005 Design, 2005
2004
Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 Design, 2004
2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
2002
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
J. Electron. Test., 2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Proceedings of the 6th European Test Workshop, 2001
2000
J. Electron. Test., 2000
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.
J. Electron. Test., 2000
Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Test Configuration Generation for FPGA Logic Cells.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the 5th European Test Workshop, 2000
TOF: a tool for test pattern generation optimization of an FPGA application oriented test.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study.
Proceedings of the 4th European Test Workshop, 1999
Proceedings of the 1999 Design, 1999
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999
1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the Field-Programmable Logic and Applications, 1998
Proceedings of the 1998 Design, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997