Michel Renovell

According to our database, Michel Renovell authored at least 178 papers between 1985 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

B-open Defect: A Novel Defect Model in FinFET Technology.

Freddy Forero, Víctor H. Champac, Michel Renovell

ACM J. Emerg. Technol. Comput. Syst., January, 2023

A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates.

Víctor H. Champac, Freddy Forero, Michel Renovell, Leonardo Miceli

Proceedings of the 24th IEEE Latin American Test Symposium, 2023

2019

Modeling and Detectability of Full Open Gate Defects in FinFET Technology.

Freddy Forero, Hector Villacorta, Michel Renovell, Víctor H. Champac

IEEE Trans. Very Large Scale Integr. Syst., 2019

Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies.

Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell

J. Electron. Test., 2019

A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells.

Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac

Proceedings of the IEEE Latin American Test Symposium, 2019

B-open: A New Defect in Nanometer Technologies due to SADP Process.

Freddy Forero, Michel Renovell, Víctor H. Champac

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

Detectability Challenges of Bridge Defects in FinFET Based Logic Cells.

Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac

J. Electron. Test., 2018

Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies.

Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell

Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

2017

Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies.

Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell

J. Electron. Test., 2017

Analysis of short defects in FinFET based logic cells.

Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology.

Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Mitigating read & write errors in STT-MRAM memories under DVS.

Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras

Proceedings of the 22nd IEEE European Test Symposium, 2017

Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions.

Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh

Proceedings of the 22nd IEEE European Test Symposium, 2017

Spot defect modeling: Past and evolution.

Michel Renovell

Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2016

Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations.

Jesús Moreno, Michel Renovell, Víctor H. Champac

IEEE Trans. Very Large Scale Integr. Syst., 2016

Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect.

Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell

Proceedings of the 17th Latin-American Test Symposium, 2016

Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations.

Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Behavior and test of open-gate defects in FinFET based cells.

Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies.

Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell

Microelectron. J., 2015

A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy.

Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Toward Adaptation of ADCs to Operating Conditions through On-chip Correction.

Vincent Kerzerho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, Serge Bernard

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Power-aware voltage tuning for STT-MRAM reliability.

Elena I. Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras

Proceedings of the 20th IEEE European Test Symposium, 2015

Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell.

Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Sram cell stability metric under transient voltage noise.

Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras

Microelectron. J., 2014

Editorial.

Serge Bernard, Patrick Garda, Michel Renovell

Microelectron. J., 2014

Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements.

Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell

Microelectron. J., 2014

Testing for gate oxide short defects using the detectability interval paradigm.

Jean-Marc Gallière, Florence Azaïs, Mariane Comte, Michel Renovell

it Inf. Technol., 2014

Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing.

Syhem Larguech, Florence Azaïs, Serge Bernard, Vincent Kerzerho, Mariane Comte, Michel Renovell

Proceedings of the 15th Latin American Test Workshop, 2014

Solutions for the self-adaptation of communicating systems in operation.

Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

DTIS 2014 foreword.

Ioannis Voyiatzis, Michel Renovell, Mohamed Masmoudi, Paolo Prinetto, Giorgio Di Natale

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

New implementions of predictive alternate analog/RF test with augmented model redundancy.

Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC.

Vincent Kerzerho, Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, Chuan Shan, G. Bontorin, Michel Renovell

Microelectron. J., 2013

Accurate and efficient analytical electrical model of antenna for NFC applications.

Mouhamadou Dieng, Mariane Comte, Serge Bernard, Vincent Kerzerho, Florence Azaïs, Michel Renovell, Thibault Kervaon, Paul-Henri Pugliesi-Conti

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays.

Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Jie Jiang, Ilia Polian, Bernd Becker

Proceedings of the 14th Latin American Test Workshop, 2013

Implementing model redundancy in predictive alternate test to improve test confidence.

Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell

Proceedings of the 18th IEEE European Test Symposium, 2013

MIRID: Mixed-Mode IR-Drop Induced Delay Simulator.

Jie Jiang, Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Ilia Polian

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Smart selection of indirect parameters for DC-based alternate RF IC testing.

Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Michel Renovell, Vincent Kerzerho, Olivier Potin, Christophe Kelma

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Low voltage testing for interconnect opens under process variations.

Jesús Moreno, Víctor H. Champac, Michel Renovell

Proceedings of the 13th Latin American Test Workshop, 2012

Making predictive analog/RF alternate test strategy independent of training set size.

Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell

Proceedings of the 2012 IEEE International Test Conference, 2012

2011

Digital Test Method for Embedded Converters with Unknown-Phase Harmonics.

Vincent Kerzerho, Mariane Comte, Florence Azaïs, Philippe Cauvet, Serge Bernard, Michel Renovell

J. Electron. Test., 2011

A new methodology for realistic open defect detection probability evaluation under process variations.

Jesús Moreno, Víctor H. Champac, Michel Renovell

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Influence of parasitic memory effect on single-cell faults in SRAMs.

Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric.

Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Editorial.

Mohamed Masmoudi, Michel Renovell

Microelectron. J., 2010

Parasitic memory effect in CMOS SRAMs.

Sandra Irobi, Zaid Al-Ars, Michel Renovell

Proceedings of the 5th International Design and Test Workshop, 2010

2009

SUPERB: Simulator utilizing parallel evaluation of resistive bridges.

Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian

ACM Trans. Design Autom. Electr. Syst., 2009

Functional Testing of Processor Cores in FPGA-Based Applications.

Mariusz Wegrzyn, Franc Novak, Anton Biasizzo, Michel Renovell

Comput. Informatics, 2009

An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.

Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A multi-converter DFT technique for complex SIP: Concepts and validation.

Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions.

Florence Azaïs, Yves Bertrand, Michel Renovell

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator.

Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Michel Renovell, Mariane Comte, Omar Chakib

VLSI Design, 2008

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.

Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring.

Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.

Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker

Proceedings of the 13th European Test Symposium, 2008

2007

Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC.

Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell

IET Comput. Digit. Tech., 2007

Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis.

Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell

J. Electron. Test., 2007

Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation.

Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.

Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell

Proceedings of the 12th European Test Symposium, 2007

System-in-Package, a Combination of Challenges and Solutions.

Philippe Cauvet, Serge Bernard, Michel Renovell

Proceedings of the 12th European Test Symposium, 2007

SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges.

Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker

Proceedings of the 16th Asian Test Symposium, 2007

Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits.

Florence Azaïs, Laurent Larguier, Michel Renovell

Proceedings of the 16th Asian Test Symposium, 2007

2006

Simulating Resistive-Bridging and Stuck-At Faults.

Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

J. Electron. Test., 2006

Automatic Test Pattern Generation for Resistive Bridging Faults.

Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker

J. Electron. Test., 2006

A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs.

Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell

IEEE Des. Test Comput., 2006

Functional Test of Field Programmable Analog Arrays.

Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Electrical Behavior of GOS Fault affected Domino Logic Cell.

Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency.

Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker

Proceedings of the 15th Asian Test Symposium, 2006

Delta-IDDQ Testing of Resistive Short Defects.

Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker

Proceedings of the 15th Asian Test Symposium, 2006

2005

Built-in self-test of global interconnects of field programmable analog arrays.

Antonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell

Microelectron. J., 2005

Delay Testing Viability of Gate Oxide Short Defects.

Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand

J. Comput. Sci. Technol., 2005

Guest Editorial.

Adoración Rueda, Michel Renovell, José Luis Huertas

J. Electron. Test., 2005

Modeling Feedback Bridging Faults with Non-Zero Resistance.

Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker

J. Electron. Test., 2005

Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

J. Electron. Test., 2005

Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks.

Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell

J. Electron. Test., 2005

A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters.

Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell

J. Electron. Test., 2005

Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications.

Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell

J. Electron. Test., 2005

Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.

Ilia Polian, Sandip Kundu, Jean-Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays.

Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2004

A New FPGA for DSP Applications Integrating BIST Capabilities.

Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell

J. Electron. Test., 2004

Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors.

Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell

J. Electron. Test., 2004

Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure.

Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell

J. Electron. Test., 2004

A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs.

Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.

Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

An Approach to the Built-In Self-Test of Field Programmable Analog Arrays.

Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Testing the Configurable Analog Blocks of Field Programmable Analog Arrays.

Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Scan Design and Secure Chip.

David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

Proceedings of the 9th European Test Symposium, 2004

High Quality TPG for Delay Faults in Look-Up Tables of FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Analysis and Attenuation Proposal in Ground Bounce.

Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

A-to-D converters static error detection from dynamic parameter measurement.

Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell

Microelectron. J., 2003

Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs.

Michel Renovell

J. Circuits Syst. Comput., 2003

Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short.

Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand

J. Electron. Test., 2003

On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST.

Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell

J. Electron. Test., 2003

Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test.

Uros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell

IEEE Des. Test Comput., 2003

An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs.

Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei

IEEE Des. Test Comput., 2003

A New Methodology For ADC Test Flow Optimization.

Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Defect Analysis for Delay-Fault BIST in FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Requirements for delay testing of look-up tables in SRAM-based FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

Proceedings of the 8th European Test Workshop, 2003

Delay Testing of MOS Transistor with Gate Oxide Short.

Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Improving Defect Detection in Static-Voltage Testing.

Michel Renovell, Florence Azaïs, Yves Bertrand

IEEE Des. Test Comput., 2002

A Structural Test Methodology for SRAM-Based FPGAs.

Michel Renovell

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Estimating Static Parameters of A-to-D Converters from Spectral Analysis.

Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell, Marcelo Lubaszewski

Proceedings of the 3rd Latin American Test Workshop, 2002

Modeling gate oxide short defects in CMOS minimum transistors.

Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand

Proceedings of the 7th European Test Workshop, 2002

A high accuracy triangle-wave signal generator for on-chip ADC testing.

Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell

Proceedings of the 7th European Test Workshop, 2002

Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA.

Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

On the detectability of CMOS floating gate transistor faults.

André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A Discussion on Test Pattern Generation for FPGA - Implemented Circuits.

Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian

J. Electron. Test., 2001

Guest Editorial.

Michel Renovell

J. Electron. Test., 2001

Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST.

Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell

J. Electron. Test., 2001

A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs.

Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell

J. Electron. Test., 2001

A Low-Cost Adaptive Ramp Generator for Analog BIST Applications.

Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Electrical Analysis of Gate Oxide Short in MOS Technologies.

Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand

Proceedings of the 2nd Latin American Test Workshop, 2001

On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area.

Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell

Proceedings of the 2nd Latin American Test Workshop, 2001

Boolean and current detection of MOS transistor with gate oxide short.

Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

IS-FPGA : a new symmetric FPGA architecture with implicit scan.

Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects.

Michel Renovell

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.

Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell

Proceedings of the SOC Design Methodologies, 2001

Analog BIST Generator for ADC Testing.

Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Implementation of a linear histogram BIST for ADCs.

Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Testing the Local Interconnect Resources of SRAM-Based FPGA's.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

J. Electron. Test., 2000

An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

J. Electron. Test., 2000

Combining Functional and Structural Approaches for Switched-Current Circuit Testing.

Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand

J. Electron. Test., 2000

Hardware Resource Minimization for Histogram-Based ADC BIST.

Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits.

Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Test Configuration Generation for FPGA Logic Cells.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 1st Latin American Test Workshop, 2000

On the Temperature Dependencies of Analog BIST.

Luigi Carro, Michel Renovell, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs

Proceedings of the 1st Latin American Test Workshop, 2000

Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital Converters.

Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell

Proceedings of the 1st Latin American Test Workshop, 2000

Different experiments in test generation for XILINX FPGAs.

Michel Renovell, Yervant Zorian

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A Specific Test Methodology for Symmetric SRAM-Based FPGAs.

Michel Renovell

Proceedings of the Field-Programmable Logic and Applications, 2000

Analyzing the test generation problem for an application-oriented test of FPGAs.

Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian

Proceedings of the 5th European Test Workshop, 2000

Towards an ADC BIST scheme using the histogram test technique.

Florence Azaïs, Serge Bernard, Y. Betrand, Michel Renovell

Proceedings of the 5th European Test Workshop, 2000

Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte.

Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski

Proceedings of the 2000 Design, 2000

TOF: a tool for test pattern generation optimization of an FPGA application oriented test.

Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

TI-BIST: a temperature independent analog BIST for switched-capacitor filters.

Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

SRAM-Based FPGAs: Testing the Embedded RAM Modules.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

J. Electron. Test., 1999

Detection of Defects Using Fault Model Oriented Test Sequences.

Michel Renovell, Florence Azaïs, Yves Bertrand

J. Electron. Test., 1999

Optimal conditions for Boolean and current detection of floating gate faults.

Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 4th European Test Workshop, 1999

Functional and structural testing of switched-current circuits.

Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand

Proceedings of the 4th European Test Workshop, 1999

Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 1999 Design, 1999

Minimizing the Number of Test Configurations for Different FPGA Families.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Testing the Interconnect of RAM-Based FPGAs.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

IEEE Des. Test Comput., 1998

Design-For-Testability for Switched-Current Circuits.

Florence Azaïs, Michel Renovell, Yves Bertrand, J.-C. Bodin

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing.

Michel Renovell, Salvador Mir, F. Azaïs M. Lubaszewsk, Yves Bertrand

Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

SRAM-based FPGAs: A Structural Test Approach.

Michel Renovell

Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

SRAM-based FPGA's: testing the LUT/RAM modules.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel).

Karl-Erwin Großpietsch, Jacob A. Abraham, Johannes Maier, Hans-Dieter Kochs, Michel Renovell

Proceedings of the Digest of Papers: FTCS-28, 1998

SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the Field-Programmable Logic and Applications, 1998

RAM-Based FPGA's: A Test Approach for the Configurable Logic.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 1998 Design, 1998

Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits.

Michel Renovell, Florence Azaïs, Yves Bertrand

Proceedings of the 1998 Design, 1998

Novel Technique for Testing FPGAs.

Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi

Proceedings of the 1998 Design, 1998

SRAM-Based FPGA's: Testing the Interconnect/Logic Interface.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

BISTing Switched-Current Circuits.

Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Microsystems Testing: A Challenge.

Michel Renovell

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Testing for Floating Gates Defects in CMOS Circuits.

Sumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs.

Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Test of RAM-based FPGA: methodology and application to the interconnect.

Michel Renovell, Joan Figueras, Yervant Zorian

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Test Strategy Sensitivity to Defect Parameters.

Michel Renovell, Yves Bertrand

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

On-chip analog output response compaction.

Michel Renovell, Florence Azaïs, Yves Bertrand

Proceedings of the European Design and Test Conference, 1997

Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

Bridging fault coverage improvement by power supply control.

Michel Renovell, P. Huc, Yves Bertrand

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

The multi-configuration: A DFT technique for analog circuits.

Michel Renovell, Florence Azaïs, Yves Bertrand

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault.

Michel Renovell, P. Huc, Yves Bertrand

Proceedings of the Dependable Computing, 1996

1995

Current testing in dynamic CMOS circuits.

Joan Figueras, Michel Renovell

J. Electron. Test., 1995

The concept of resistance interval: a new parametric model for realistic resistive bridging fault.

Michel Renovell, P. Huc, Yves Bertrand

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Serial transistor network modeling for bridging fault simulation.

Michel Renovell, P. Huc, Yves Bertrand

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

A design-for-test technique for multistage analog circuits.

Michel Renovell, Florence Azaïs, Yves Bertrand

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Test configurations to enhance the testability of sequential circuits.

S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

CMOS bridging fault modeling.

Michel Renovell, P. Huc, Yves Bertrand

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds.

Michel Renovell, P. Huc, Yves Bertrand

Proceedings of the Dependable Computing, 1994

1993

A DFT Technique to Improve ATPG Efficiency for Sequential Circuits.

Yves Bertrand, Frédéric Bancel, Michel Renovell

Proceedings of the Sixth International Conference on VLSI Design, 1993

Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits.

Yves Bertrand, Frédéric Bancel, Michel Renovell

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Current Testing Viability in Dynamic CMOS Circuits.

Michel Renovell, Joan Figueras

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992

Electrical analysis and modeling of floating-gate fault.

Michel Renovell, Gaston Cambon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs.

Michel Renovell, M. Ildevert, Yves Bertrand

Proceedings of the Fifth International Conference on VLSI Design, 1992

1985

FSPICE: a tool for fault modelling in MOS circuits.

Michel Renovell, Gaston Cambon, Daniel Auvergne

Integr., 1985