Peng Wang

According to our database, Peng Wang authored at least 6 papers between 2015 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A 1-GS/s 12-bit Pipelined-SAR ADC With Dither-Based Background Calibration of Interstage Gain and Comparator Offset in 28-nm CMOS.

Peng Wang, Nan Wu, Fule Li, Zhihua Wang

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026

2025

A Single-Channel 8-bit 1.6-GS/s Alternate-Comparator SAR ADC With Dither-Based Background Offset Calibration in 28-nm CMOS.

Peng Wang, Fule Li, Zhihua Wang

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2025

A High-Speed High-Precision Comparator with Offset Calibration for SHA_less Pipeline ADCs.

Shuoxiong Yang, Dejian Li, Peng Wang, Fule Li, Zhihua Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A SHA-Less Front-end Stage Structure Suitable for Time-Interleaved Pipeline ADC.

Meng Ni, Peng Wang, Fule Li, Hanjun Jiang, Zhihua Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2022

A statistics-based background capacitor mismatch calibration algorithm for SAR ADC.

Zhiqiang Luo, Peng Wang, Fule Li, Chun Zhang, Zhihua Wang

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2015

A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS.

Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Peng Wang, Wen Jia, Chun Zhang, Zhihua Wang

Proceedings of the ESSCIRC Conference 2015, 2015