Péter Földesy

According to our database, Péter Földesy authored at least 19 papers between 1997 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

Non-Contact Vital-Sign Monitoring System for Premature Infants in Neonatal Intensive Care Units.

Péter Földesy, Imre Jánoki, Ákos Zarándy, Péter Pázmány

ERCIM News, 2020

Multi-Level Optimization for Enabling Life Critical Visual Inspections of Infants in Resource Limited Environment.

Ákos Zarándy, Péter Földesy, Ádám Nagy, Imre Jánoki, Dániel Terbe, Máté Siket, Miklós Szabó, Judit Varga

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2013

A hierarchical vision processing architecture oriented to 3D integration of smart camera chips.

Ricardo Carmona-Galán, Ákos Zarándy, Csaba Rekeczky, Péter Földesy, Alberto Rodríguez-Pérez, Carlos M. Domínguez-Matas, Jorge Fernández-Berni, Gustavo Liñán Cembrano, Maria Belen Pérez-Verdú, Zoltán Kárász, Manuel Suárez-Cambre, Víctor Manuel Brea Sánchez, Tamás Roska, Ángel Rodríguez-Vázquez

J. Syst. Archit., 2013

2012

Characterization of silicon field effect transistor sub-THz detectors for imaging systems.

Péter Földesy

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Test and configuration architecture of a sub-THz CMOS detector array.

Péter Földesy, Domonkos Gergelyi, Csaba Fuzy, Gergely Károlyi

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2009

3D multi-layer vision architecture for surveillance and reconnaissance applications.

Péter Földesy, Ricardo Carmona-Galán, Ákos Zarándy, Csaba Rekeczky, Ángel Rodríguez-Vázquez, Tamás Roska

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008

Configurable 3D-integrated focal-plane cellular sensor-processor array architecture.

Péter Földesy, Ákos Zarándy, Csaba Rekeczky

Int. J. Circuit Theory Appl., 2008

2007

High performance processor array for image processing.

Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

3D integrated scalable focal-plane processor array.

Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

Digital implementation of cellular sensor-computers.

Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska

Int. J. Circuit Theory Appl., 2006

2005

Various implementations of topographic, sensory, cellular wave computers.

Ákos Zarándy, Péter Földesy, Péter Szolgay, Szabolcs Tõkés, Csaba Rekeczky, Tamás Roska

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Per-pixel integration time controlled image sensor.

Ákos Zarándy, Péter Földesy, Tamás Roska

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2003

The New Framework Of Applications: The Aladdin System.

Ákos Zarándy, Csaba Rekeczky, Péter Földesy, István Szatmári

J. Circuits Syst. Comput., 2003

PDE-Based Histogram Modification With Embedded Morphological Processing Of The Level-Sets.

György Cserey, Csaba Rekeczky, Péter Földesy

J. Circuits Syst. Comput., 2003

2002

A behavioural modelling technique for visual microprocessor mixed-signal VLSI chips.

Péter Földesy, Ángel Rodríguez-Vázquez

Int. J. Circuit Theory Appl., 2002

2001

Computing on silicon with trigger waves: experiments on CNN-UM chips.

Csaba Rekeczky, István Szatmári, Péter Földesy

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

An analogic CNN engine board with the 64×64 analog I/O CNN-UM chip.

István Szatmári, Ákos Zarándy, Péter Földesy, László Kék

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Implementation of non-linear templates using a decomposition technique by a 0.5 μm CMOS CNN universal chip.

Gustavo Liñán, Péter Földesy, A. Rodrignez-Vazquez, Servando Espejo, Rafael Domínguez-Castro

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1997

A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage.

Rafael Domínguez-Castro, Servando Espejo, Ángel Rodríguez-Vázquez, Ricardo Carmona, Péter Földesy, Ákos Zarándy, Péter Szolgay, Tamás Szirányi, Tamás Roska

IEEE J. Solid State Circuits, 1997