Ricardo Carmona-Galán

Orcid: 0000-0002-4230-3988

According to our database1, Ricardo Carmona-Galán authored at least 123 papers between 1996 and 2024.

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Bibliography

2024
A novel 10T SRAM bit-cell with high static noise margin and low power consumption for binary In-Memory Computing.
Proceedings of the 14th IEEE Annual Computing and Communication Workshop and Conference, 2024

2023
Flydeling: Streamlined Performance Models for Hardware Acceleration of CNNs through System Identification.
ACM Trans. Model. Perform. Evaluation Comput. Syst., September, 2023

An Analog-to-Information Architecture for Single-Chip Sensor-Processor Inference System.
Proceedings of the IEEE International Conference on Metrology for eXtended Reality, 2023

Hardware-Efficient Random-Modulation ΣΔ ADC for Per-Column CS Generation in Vision Sensor.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
Special Issue on Embedded Vision Architectures for Machine Learning.
J. Signal Process. Syst., 2022

An Efficient TDC Using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA.
IEEE Trans. Instrum. Meas., 2022

Architecture-Level Optimization on Digital Silicon Photomultipliers for Medical Imaging.
Sensors, 2022

An Architecture for On-Chip Face Recognition in a Compressive Image Sensor.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

Accurate Face Recognition on Highly Compressed Samples.
Proceedings of the 16th International Conference on Signal-Image Technology & Internet-Based Systems, 2022

2021
A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA.
Sensors, 2021

A Novel Approach for Measurement Throughput Maximization in FPGA-based TDCs.
Proceedings of the 7th International Conference on Event-Based Control, 2021

2020
Compressive Imaging Using RIP-Compliant CMOS Imager Architecture and Landweber Reconstruction.
IEEE Trans. Circuits Syst. Video Technol., 2020

Comparison between Digital Tone-Mapping Operators and a Focal-Plane Pixel-Parallel Circuit.
Signal Process. Image Commun., 2020

PreVIous: A Methodology for Prediction of Visual Inference Performance on IoT Devices.
IEEE Internet Things J., 2020

VersaTile Convolutional Neural Network Mapping on FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Photon-Detection Timing-Jitter Model in Verilog-A.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Vertically Stacked CMOS-Compatible Photodiodes for Scanning Electron Microscopy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Cellular-Neural-Network Focal-Plane Processor as Pre-Processor for ConvNet Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020


Limitation of SPADs quantum efficiency due to the dopants concentration gradient.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
On the Correlation of CNN Performance and Hardware Metrics for Visual Inference on a Low-Cost CPU-based Platform.
Proceedings of the International Conference on Systems, Signals and Image Processing, 2019

ToF Estimation Based on Compressed Real-Time Histogram Builder for SPAD Image Sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

CNN Performance Prediction on a CPU-based Edge Platform.
Proceedings of the 13th International Conference on Distributed Smart Cameras, 2019

A survey on FPGA-based high-resolution TDCs.
Proceedings of the 13th International Conference on Distributed Smart Cameras, 2019

Impact of CNNs Pooling Layer Implementation on FPGAs Accelerator Design.
Proceedings of the 13th International Conference on Distributed Smart Cameras, 2019

Low-Noise and High-Efficiency Near-IR SPADs in 110nm CIS Technology.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2018
Asynchronous Spiking Pixel With Programmable Sensitivity to Illumination.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Applications of event-based image sensors - Review and analysis.
Int. J. Circuit Theory Appl., 2018

Guest editorial: Special issue on computational image sensors and smart camera hardware.
Int. J. Circuit Theory Appl., 2018

Optimum Selection of DNN Model and Framework for Edge Inference.
IEEE Access, 2018

Color Tone-Mapping Circuit for a Focal-Plane Implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Live Demonstration: Low-Power Low-Cost Cyber-Physical System for Bird Monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Experimentally-Validated Verilog-A SPAD Model Extracted from TCAD Simulation.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

CMOS-SPAD Camera Prototype for Single-Sensor 2D/3D Imaging.
Proceedings of the 12th International Conference on Distributed Smart Cameras, 2018

On-The-Fly Deployment of Deep Neural Networks on Heterogeneous Hardware in a Low-Cost Smart Camera.
Proceedings of the 12th International Conference on Distributed Smart Cameras, 2018

On the characterization of light sources irradiation profiles with an HDR image sensor.
Proceedings of the 12th International Conference on Distributed Smart Cameras, 2018

Results of 'iCaveats', a Project on the Integration of Architectures and Components for Embedded Vision.
Proceedings of the 12th International Conference on Distributed Smart Cameras, 2018

Concurrent focal-plane generation of compressed samples from time-encoded pixel values.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Optimum Network/Framework Selection from High-Level Specifications in Embedded Deep Learning Vision Applications.
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2018

2017
Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Gaussian Pyramid: Comparative Analysis of Hardware Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Compensation of PVT Variations in ToF Imagers with In-Pixel TDC.
Sensors, 2017

Low-Power CMOS Vision Sensor for Gaussian Pyramid Extraction.
IEEE J. Solid State Circuits, 2017

A Wide Linear Dynamic Range Image Sensor Based on Asynchronous Self-Reset and Tagging of Saturation Events.
IEEE J. Solid State Circuits, 2017

Special issue on computational image sensors and smart camera hardware.
Int. J. Circuit Theory Appl., 2017

Photon counting and direct ToF camera prototype based on CMOS SPADs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Live demonstration: Photon counting and direct ToF camera prototype based on CMOS SPADs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Pipeline AER arbitration with event aging.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A sun sensor implemented with an asynchronous luminance vision sensor.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

In the quest of vision-sensors-on-chip: Pre-processing sensors for data reduction.
Proceedings of the Image Sensors and Imaging Systems 2017, 2017

2016
Single-Exposure HDR Technique Based on Tunable Balance Between Local and Global Adaptation.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Special issue on architectures of smart cameras for real-time applications.
J. Real Time Image Process., 2016

Compact CMOS active quenching/recharge circuit for SPAD arrays.
Int. J. Circuit Theory Appl., 2016

High-level Performance Evaluation of Object Detection based on Massively Parallel Focal-plane Acceleration Requiring Minimum Pixel Area Overhead.
Proceedings of the 11th Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications (VISIGRAPP 2016), 2016

Hardware-aware performance evaluation for the co-design of image sensors and vision algorithms.
Proceedings of the 13th International Conference on Synthesis, 2016

In-pixel voltage-controlled ring-oscillator for phase interpolation in ToF image sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Live demonstration: Single-exposure HDR image acquisition based on tunable balance between local and global adaptation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

HDR image sensor with linear response and asynchronous detection of saturation: Demo.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

Image Sensing Scheme Enabling Fully-Programmable Light Adaptation and Tone Mapping with a Single Exposure: Demo.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

Pixel-wise parameter adaptation for single-exposure extension of the image dynamic range.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

Focal-Plane Scale Space Generation with a 6T Pixel Architecture.
Proceedings of the Image Sensors and Imaging Systems 2016, 2016

A high dynamic range linear vision sensor with event asynchronous and frame-based synchronous operation.
Proceedings of the Image Sensors and Imaging Systems 2016, 2016

2015
Bottom-up performance analysis of focal-plane mixed-signal hardware for Viola-Jones early vision tasks.
Int. J. Circuit Theory Appl., 2015

A More Efficient Parallel Method For Neighbour Search Using CUDA.
Proceedings of the Workshop on Virtual Reality Interaction and Physical Simulation, 2015

Real-time single-exposure ROI-driven HDR adaptation based on focal-plane reconfiguration.
Proceedings of the Real-Time Image and Video Processing 2015, 2015

On the calibration of a SPAD-based 3D imager with in-pixel TDC using a time-gated technique.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Live demonstration: Gaussian pyramid extraction with a CMOS vision sensor.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

On the design of a sparsifying dictionary for compressive image feature extraction.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Hardware-oriented feature extraction based on compressive sensing.
Proceedings of the 9th International Conference on Distributed Smart Camera, 2015

CMOS image sensor architecture for focal plane early vision processing.
Proceedings of the 9th International Conference on Distributed Smart Camera, 2015

A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measurement.
Proceedings of the Image Sensors and Imaging Systems 2015, 2015

A high dynamic range image sensor with linear response based on asynchronous event detection.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
Focal-Plane Sensing-Processing: A Power-Efficient Approach for the Implementation of Privacy-Aware Networked Visual Sensors.
Sensors, 2014

Form factor improvement of smart-pixels for vision sensors through 3-D vertically-integrated technologies.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Wide range 8ps incremental resolution time interval generator based on FPGA technology.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Demo: A Prototype Vision Sensor for Real-time Focal-plane Obfuscation through Tunable Pixelation.
Proceedings of the International Conference on Distributed Smart Cameras, 2014

A QVGA Vision Sensor with Multi-functional Pixels for Focal-Plane Programmable Obfuscation.
Proceedings of the International Conference on Distributed Smart Cameras, 2014

A 26.5 nJ/px 2.64 Mpx/s CMOS vision sensor for Gaussian pyramid extraction.
Proceedings of the ESSCIRC 2014, 2014

Smart imaging for power-efficient extraction of Viola-Jones local descriptors.
Proceedings of the Image Sensors and Imaging Systems 2014, 2014

2013
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips.
J. Syst. Archit., 2013

Smart camera architecture.
J. Syst. Archit., 2013

A CMOS 8×8 SPAD array for Time-of-Flight measurement and light-spot statistics.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

An ultra-low-power voltage-mode asynchronous WTA-LTA circuit.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 176×120 pixel CMOS vision chip for Gaussian filtering with massivelly Parallel CDS and A/D-conversion.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
Ultralow-Power Processing Array for Image Enhancement and Edge Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

All-MOS implementation of RC networks for time-controlled Gaussian spatial filtering.
Int. J. Circuit Theory Appl., 2012

CMOS-3D Smart Imager Architectures for Feature Detection.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

In-pixel generation of gaussian pyramid images by block reusing in 3D-CMOS.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Power-efficient focal-plane image representation for extraction of enriched Viola-Jones features.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
FLIP-Q: A QCIF Resolution Focal-Plane Array for Low-Power Image Processing.
IEEE J. Solid State Circuits, 2011

Demo: Real-time remote reporting of active regions with Wi-FLIP.
Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

Wi-FLIP: A wireless smart camera based on a focal-plane low-power image processor.
Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

Switched-capacitor networks for scale-space generation.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Image filtering by reduced kernels exploiting kernel structure and focal-plane averaging.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
In-pixel ADC for a vision architecture on CMOS-3D technology.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
On the implementation of linear diffusion in transconductance-based cellular nonlinear networks.
Int. J. Circuit Theory Appl., 2009

A VLSI-oriented and Power-efficient Approach for Dynamic Texture Recognition Applied to Smoke Detection.
Proceedings of the VISAPP 2009 - Proceedings of the Fourth International Conference on Computer Vision Theory and Applications, Lisboa, Portugal, February 5-8, 2009, 2009

3D multi-layer vision architecture for surveillance and reconnaissance applications.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Accurate design of a MOS-based resistive network for time-controlled diffusion filtering.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2007
Performance Evaluation and Limitations of a Vision System on a Reconfigurable/Programmable Chip.
J. Univers. Comput. Sci., 2007

A Focal-Plane Image Processor for Low Power Adaptive Capture and Analysis of the Visual Stimulus.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Practical limitations to the implementation of resistive grid filtering in Cellular Neural Networks.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Robust Symmetric Multiplication for Programmable Analog VLSI Array Processing.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2004
ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Reaction-diffusion navigation robot control: from chemical to VLSI analogic processors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O.
IEEE J. Solid State Circuits, 2004

Implementing the Multilayer Retinal Model on the Complex-Cell CNN-um Chip Prototype.
Int. J. Bifurc. Chaos, 2004

A CNN-driven locally adaptive CMOS image sensor.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A bio-inspired two-layer mixed-signal flexible programmable chip for early vision.
IEEE Trans. Neural Networks, 2003

Exploration Of Spatial-Temporal Dynamic Phenomena In A 32*32-Cell Stored Program Two-Layer CNN Universal Machine Chip Prototype.
J. Circuits Syst. Comput., 2003

CMOS Realization of a 2-Layer CNN Universal Machine Chip.
Int. J. Neural Syst., 2003

Analog weight buffering strategy for CNN chips.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Retinal Processing Emulation in a Programmable 2-Layer Analog Array Processor CMOS Chip.
Proceedings of the Advances in Neural Information Processing Systems 15 [Neural Information Processing Systems, 2002

Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip.
Proceedings of the 2002 Design, 2002

2001
CMOS design of focal plane programmable array processors.
Proceedings of the 9th European Symposium on Artificial Neural Networks, 2001

1999
An 0.5-µm CMOS Analog Random Access Memory Chip for TeraOPS Speed Multimedia Video Processing.
IEEE Trans. Multim., 1999

SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips.
Int. J. Circuit Theory Appl., 1999

1997
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage.
IEEE J. Solid State Circuits, 1997

1996
A VLSI-oriented continuous-time CNN model.
Int. J. Circuit Theory Appl., 1996

A CNN Universal Chip in CMOS Technology.
Int. J. Circuit Theory Appl., 1996


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