Rafael Domínguez-Castro
Orcid: 0000-0002-9924-3410
According to our database1,
Rafael Domínguez-Castro
authored at least 36 papers
between 1993 and 2015.
Collaborative distances:
Collaborative distances:
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Bibliography
2015
Proceedings of the Image Sensors and Imaging Systems 2015, 2015
2012
High-speed global shutter CMOS machine vision sensor with high dynamic range image acquisition and embedded intelligence.
Proceedings of the Sensors, 2012
2009
Proceedings of the Spatial Temporal Patterns for Action-Oriented Perception in Roving Robots, 2009
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
IEEE J. Solid State Circuits, 2004
2003
IEEE Trans. Neural Networks, 2003
An Improved Elementary Processing Unit For High-Density CNN-Based Mixed-Signal Microprocessors For Vision.
J. Circuits Syst. Comput., 2003
Int. J. Neural Syst., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
Int. J. Circuit Theory Appl., 2002
Retinal Processing Emulation in a Programmable 2-Layer Analog Array Processor CMOS Chip.
Proceedings of the Advances in Neural Information Processing Systems 15 [Neural Information Processing Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
A processing element architecture for high-density focal plane analog programmable array processors.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip.
Proceedings of the 2002 Design, 2002
2001
Proceedings of the 9th European Symposium on Artificial Neural Networks, 2001
2000
Implementation of non-linear templates using a decomposition technique by a 0.5 μm CMOS CNN universal chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 Design, 2000
1999
MOST-Based Design and Scaling of Synaptic Interconnections in VLSI Analog Array Processing CNN Chips.
J. VLSI Signal Process., 1999
J. VLSI Signal Process., 1999
An 0.5-µm CMOS Analog Random Access Memory Chip for TeraOPS Speed Multimedia Video Processing.
IEEE Trans. Multim., 1999
SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips.
Int. J. Circuit Theory Appl., 1999
1998
Electrooptical measurement system for the DC characterization of visible detectors for CMOS-compatible vision chips.
IEEE Trans. Instrum. Meas., 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1997
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage.
IEEE J. Solid State Circuits, 1997
1996
1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
IEEE J. Solid State Circuits, August, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
1993
A Model for VLSI Implementation of CNN Image Processing Chips Using Current-mode Techniques.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993