Gustavo Liñán Cembrano

Nuno Lourenço

Nuno Horta

José M. de la Rosa

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2015

Live demonstration: Real-time high dynamic range video acquisition using in-pixel adaptive content-aware tone mapping compression.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013

A hierarchical vision processing architecture oriented to 3D integration of smart camera chips.

[BibT_eX]

[DOI]

Carlos M. Domínguez-Matas

Ákos Zarándy

Csaba Rekeczky

Péter Földesy

Alberto Rodríguez-Pérez

Víctor Manuel Brea Sánchez

Maria Belen Pérez-Verdú

Zoltán Kárász

Manuel Suárez-Cambre

Tamás Roska

J. Syst. Archit., 2013

2012

CMOS-3D Smart Imager Architectures for Feature Detection.

[BibT_eX]

[DOI]

Manuel Suarez

Víctor M. Brea

Diego Cabello

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A 148dB focal-plane tone-mapping QCIF imager.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Control and acquisition system for a High Dynamic Range CMOS Image Sensor.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A 176×144 148dB adaptive tone-mapping imager.

[BibT_eX]

[DOI]

Proceedings of the Sensors, 2012

2011

Demo: Real-time remote reporting of active regions with Wi-FLIP.

[BibT_eX]

[DOI]

Ákos Zarándy

Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

Wi-FLIP: A wireless smart camera based on a focal-plane low-power image processor.

[BibT_eX]

[DOI]

Ákos Zarándy

Carlos M. Domínguez-Matas

Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

2010

In-pixel ADC for a vision architecture on CMOS-3D technology.

[BibT_eX]

[DOI]

Manuel Suarez

Víctor M. Brea

Ricardo Carmona

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Integrated Circuitry to Detect Slippage Inspired by Human Skin and Artificial Retinas.

[BibT_eX]

[DOI]

Rocío Maldonado-López

Fernando Vidal-Verdú

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

APS design alternatives in 0.18μm CMOS image sensor technology.

[BibT_eX]

[DOI]

Elisenda Roca

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A focal plane processor for continuous-time 1-D optical correlation applications.

[BibT_eX]

[DOI]

Luis Carranza

Betsaida Alexandre

Elisenda Roca

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2007

Focal plane processors & pixel level processing: mimicking natural vision systems to solve image processing problems.

[BibT_eX]

[DOI]

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

2006

Locust-inspired vision system on chip architecture for collision detection in automotive applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004

ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs.

[BibT_eX]

[DOI]

L. Carranza

Elisenda Roca Moreno

Francisco Jiménez-Garrido

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O.

[BibT_eX]

[DOI]

Francisco Jiménez-Garrido

IEEE J. Solid State Circuits, 2004

2003

An Improved Elementary Processing Unit For High-Density CNN-Based Mixed-Signal Microprocessors For Vision.

[BibT_eX]

[DOI]

Carlos M. Domínguez-Matas

J. Circuits Syst. Comput., 2003

A modem in CMOS technology for data communication on the low-voltage power line.

[BibT_eX]

[DOI]

Oscar Guerra

Sara Escalera

José M. García-González

Rocío del Río

Manuel Delgado-Restituto

Integr., 2003

ACE16k: A 128x128 Focal Plane Analog Processor with Digital I/O.

[BibT_eX]

[DOI]

Int. J. Neural Syst., 2003

Analog weight buffering strategy for CNN chips.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 1000FPS@128×128 vision processor with 8-bit digitized I/O.

[BibT_eX]

[DOI]

Rafael Castro-López

Proceedings of the ESSCIRC 2003, 2003

2002

ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2002

Mismatch-induced tradeoffs and scalability of mixed-signal vision chips.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A processing element architecture for high-density focal plane analog programmable array processors.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

CMOS design of focal plane programmable array processors.

[BibT_eX]

[DOI]

Proceedings of the 9th European Symposium on Artificial Neural Networks, 2001

2000

Implementation of non-linear templates using a decomposition technique by a 0.5 μm CMOS CNN universal chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

A Programmable Imager for Very High Speed Cellular Signal Processing.

[BibT_eX]

[DOI]

Elisenda Roca

J. VLSI Signal Process., 1999

SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips.

[BibT_eX]

[DOI]

Ricardo Carmona

Ignacio Garcia-Vargas

Int. J. Circuit Theory Appl., 1999

1998

A 64×64 CNN universal chip with analog and digital I/O.

[BibT_eX]

[DOI]