Peter Schvan

According to our database, Peter Schvan authored at least 20 papers between 1997 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator.

Naftali Weiss, Gregory Cooke, Peter Schvan, Pascal Chevalier, Andreia Cathelin, Sorin P. Voinigescu

Proceedings of the 47th ESSCIRC 2021, 2021

2020

Data Converter Interleaving: Current Trends and Future Perspectives.

Christian Schmidt, Hiroshi Yamazaki, Gregory Raybon, Peter Schvan, Erwan Pincemin, S. J. Ben Yoo, Daniel J. Blumenthal, Takayuki Mizuno, Robert Elschner

IEEE Commun. Mag., 2020

2019

Design of a 55-nm SiGe BiCMOS 5-bit Time-Interleaved Flash ADC for 64-Gbd 16-QAM Fiberoptics Applications.

Alireza Zandieh, Peter Schvan, Sorin P. Voinigescu

IEEE J. Solid State Circuits, 2019

Coherent Transceiver for High Speed Optical Communications: Opportunities and Challenges.

Sebastien Blais, Yuriy M. Greshishchev, Peter Schvan, Ian Betty, Douglas McGhan

Proceedings of the 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019

2018

A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud Applications.

Alireza Zandieh, Peter Schvan, Sorin P. Voinigescu

Proceedings of the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018

2016

55-nm SiGe BiCMOS Distributed Amplifier Topologies for Time-Interleaved 120-Gb/s Fiber-Optic Receivers and Transmitters.

James Hoffman, Stefan Shopov, Pascal Chevalier, Andreia Cathelin, Peter Schvan, Sorin P. Voinigescu

IEEE J. Solid State Circuits, 2016

2011

A 2.4-V_pp 60-Gb/s CMOS Driver With Digitally Variable Amplitude and Pre-Emphasis Control at Multiple Peaking Frequencies.

Ricardo Andres Aroca, Peter Schvan, Sorin P. Voinigescu

IEEE J. Solid State Circuits, 2011

A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory.

Yuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang, Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben-Hamida, Robert Gibbins, Peter Schvan

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 40GS/s 6b ADC in 65nm CMOS.

Yuriy M. Greshishchev, Jorge Aguirre, Marinette Besson, Robert Gibbins, Chris Falt, Philip Flemke, Naim Ben-Hamida, Daniel Pollex, Peter Schvan, Shing-Chi Wang

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 40 Gb/s transimpedance amplifier in 65 nm CMOS.

Samira Bashiri, Calvin Plett, Jorge Aguirre, Peter Schvan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Clock recovery for a 40 Gb/s QPSK optical receiver.

Naim Ben-Hamida, John Sitch, Philip Flemke, Daniel Pollex, Peter Schvan, Yuriy M. Greshishchev, Shing-Chi Wang, Chris Falt

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

A 24GS/s 6b ADC in 90nm CMOS.

Peter Schvan, Jérôme Bach, Chris Falt, Philip Flemke, Robert Gibbins, Yuriy M. Greshishchev, Naim Ben-Hamida, Daniel Pollex, John Sitch, Shing-Chi Wang, John Wolczanski

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio.

Terry Yao, Michael Q. Gordon, Keith K. W. Tang, Kenneth H. K. Yau, Ming-Ta Yang, Peter Schvan, Sorin P. Voinigescu

IEEE J. Solid State Circuits, 2007

Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS.

Theodoros Chalvatzis, Kenneth H. K. Yau, Ricardo Andres Aroca, Peter Schvan, Ming-Ta Yang, Sorin P. Voinigescu

IEEE J. Solid State Circuits, 2007

CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples.

Sorin P. Voinigescu, Sean T. Nicolson, Mehdi Khanpour, Keith K. W. Tang, Kenneth H. K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, George V. Eleftheriades, Peter Schvan, Ming-Ta Yang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

A 22GS/s 5b adc in 0.13µm SiGe BiCMOS.

Peter Schvan, Daniel Pollex, Shing-Chi Wang, Chris Falt, Naim Ben-Hamida

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2000

A fully integrated SiGe receiver IC for 10-Gb/s data rate.

Yuriy M. Greshishchev, Peter Schvan, Jonathan L. Showell, Mu-Liang Xu, Jugnu J. Ojha, Jonathan E. Rogers

IEEE J. Solid State Circuits, 2000

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application.

Yuriy M. Greshishchev, Peter Schvan

IEEE J. Solid State Circuits, 2000

1999

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBT limiting amplifier.

Yuriy M. Greshishchev, Peter Schvan

IEEE J. Solid State Circuits, 1999

1997

A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design.

Sorin P. Voinigescu, Michael C. Maliepaard, Jonathan L. Showell, Greg E. Babcock, David Marchesan, Michael Schroter, Peter Schvan, David L. Harame

IEEE J. Solid State Circuits, 1997