Phillip H. Jones

According to our database1, Phillip H. Jones authored at least 50 papers between 2004 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory Exploits.
IEEE Trans. Computers, 2018

HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

An FPGA-based Hardware Accelerator for Iris Segmentation.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
The design and integration of a software configurable and parallelized coprocessor architecture for LQR control.
J. Parallel Distrib. Comput., 2017

A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

An embedded scalable linear model predictive hardware-based controller using ADMM.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
A Reconfigurable Architecture for the Detection of Strongly Connected Components.
TRETS, 2016

RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing.
IEEE Trans. Parallel Distrib. Syst., 2016

Parameterizable FPGA-Based Kalman Filter Coprocessor Using Piecewise Affine Modeling.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Evidence-based planning to broaden the participation of women in electrical and computer engineering.
Proceedings of the 2016 IEEE Frontiers in Education Conference, 2016

2015
A Fault-Aware Toolchain Approach for FPGA Fault Tolerance.
ACM Trans. Design Autom. Electr. Syst., 2015

A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns.
SIGARCH Computer Architecture News, 2015

An FPGA Architecture for the Recovery of WPA/WPA2 Keys.
Journal of Circuits, Systems, and Computers, 2015

A Scalable Unsegmented Multiport Memory for FPGA-Based Systems.
Int. J. Reconfig. Comp., 2015

A software configurable and parallelized coprocessor architecture for LQR control.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Accelerating all-pairs shortest path using a message-passing reconfigurable architecture.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A project-based embedded systems design course using a reconfigurable SoC platform.
Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

A software configurable coprocessor-based state-space controller.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator.
Proceedings of the IEEE International Conference on Electro/Information Technology, 2015

2014
Hardware-software architecture for priority queue management in real-time and embedded systems.
IJES, 2014

An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis.
Embedded Systems Letters, 2014

A high performance systolic architecture for k-NN classification.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Cache design for mixed criticality real-time systems.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
Hardware architectural support for control systems and sensor processing.
ACM Trans. Embedded Comput. Syst., 2013

Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms.
Proceedings of the International Conference on Computational Science, 2013

2012
An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs.
IEEE Trans. on Circuits and Systems, 2012

Improving System Predictability and Performance via Hardware Accelerated Data Structures.
Proceedings of the International Conference on Computational Science, 2012

Shepard: A fast exact match short read aligner.
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Design and evaluation of a delay-based FPGA Physically Unclonable Function.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
Characterizing Non-ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-Based Thermometers.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Teaching graphics processing and architecture using a hardware prototyping approach.
Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
Team [Ii][Ss][Uu][0-2]{4} design overview: MEMOCODE 2010 design contest.
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

CANSCID-CUDA.
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

An evaluation of a slice fault aware tool chain.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Towards Hardware Support for Common Sensor Processing Tasks.
Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Performance.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

2007
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Adaptive Thermoregulation for Applications on Reconfigurable Devices.
Proceedings of the FPL 2007, 2007

Changing Output Quality for Thermal Management.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006
An adaptive frequency control method using thermal feedback for reconfigurable hardware applications.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

A Thermal Management and Profiling Method for Reconfigurable Hardware Applications.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures.
International Journal of Parallel Programming, 2005

Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

2004
Liquid Architecture.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004


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