Joseph Zambreno

Orcid: 0000-0002-0566-5744

According to our database1, Joseph Zambreno authored at least 120 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Efficient Unmanned Aerial Systems Navigation With Collision Avoidance in Dense Urban Environments.
IEEE Trans. Intell. Transp. Syst., August, 2023

An FPGA Implementation of SipHash.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

2022
A Fast Markov Decision Process-Based Algorithm for Collision Avoidance in Urban Air Mobility.
IEEE Trans. Intell. Transp. Syst., 2022

Reverse Engineering Controller Area Network Messages Using Unsupervised Machine Learning.
IEEE Consumer Electron. Mag., 2022

2021
Benchmarking vision kernels and neural network inference accelerators on embedded platforms.
J. Syst. Archit., 2021

An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020
CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks.
J. Signal Process. Syst., 2020

SAIDuCANT: Specification-Based Automotive Intrusion Detection Using Controller Area Network (CAN) Timing.
IEEE Trans. Veh. Technol., 2020

Scalable FastMDP for Pre-departure Airspace Reservation and Strategic De-conflict.
CoRR, 2020

Towards Reverse Engineering Controller Area Network Messages Using Machine Learning.
Proceedings of the 6th IEEE World Forum on Internet of Things, 2020

Embedding Online Runtime Verification for Fault Disambiguation on Robonaut2.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2020

ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019
Survey of Automotive Controller Area Network Intrusion Detection Systems.
IEEE Des. Test, 2019

Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Automotive Intrusion Detection Based on Constant CAN Message Frequencies Across Vehicle Driving Modes.
Proceedings of the ACM Workshop on Automotive Cybersecurity, 2019

Anomaly Detection Approach Using Adaptive Cumulative Sum Algorithm for Controller Area Network.
Proceedings of the ACM Workshop on Automotive Cybersecurity, 2019

An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory Exploits.
IEEE Trans. Computers, 2018

Work-in-Progress: Real-Time Modeling for Intrusion Detection in Automotive Controller Area Network.
Proceedings of the 2018 IEEE Real-Time Systems Symposium, 2018

HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

An FPGA-based Hardware Accelerator for Iris Segmentation.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection.
Proceedings of the 47th International Conference on Parallel Processing, 2018

A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
The design and integration of a software configurable and parallelized coprocessor architecture for LQR control.
J. Parallel Distributed Comput., 2017

A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

An embedded scalable linear model predictive hardware-based controller using ADMM.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
A Reconfigurable Architecture for the Detection of Strongly Connected Components.
ACM Trans. Reconfigurable Technol. Syst., 2016

RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing.
IEEE Trans. Parallel Distributed Syst., 2016

Parameterizable FPGA-Based Kalman Filter Coprocessor Using Piecewise Affine Modeling.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

ONAC: Optimal number of active cores detector for energy efficient GPU computing.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Parallelizing Latent Semantic Indexing using an FPGA-based architecture.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Evidence-based planning to broaden the participation of women in electrical and computer engineering.
Proceedings of the 2016 IEEE Frontiers in Education Conference, 2016

2015
A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns.
SIGARCH Comput. Archit. News, 2015

Real-time simulation of dynamic vehicle models using a high-performance reconfigurable platform.
Microprocess. Microsystems, 2015

An FPGA Architecture for the Recovery of WPA/WPA2 Keys.
J. Circuits Syst. Comput., 2015

A Scalable Unsegmented Multiport Memory for FPGA-Based Systems.
Int. J. Reconfigurable Comput., 2015

A software configurable and parallelized coprocessor architecture for LQR control.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Accelerating all-pairs shortest path using a message-passing reconfigurable architecture.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A project-based embedded systems design course using a reconfigurable SoC platform.
Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

A software configurable coprocessor-based state-space controller.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

A multi-phase approach to floating-point compression.
Proceedings of the IEEE International Conference on Electro/Information Technology, 2015

k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator.
Proceedings of the IEEE International Conference on Electro/Information Technology, 2015

Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014
Hardware Architecture for Video Authentication Using Sensor Pattern Noise.
IEEE Trans. Circuits Syst. Video Technol., 2014

Hardware-software architecture for priority queue management in real-time and embedded systems.
Int. J. Embed. Syst., 2014

An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis.
IEEE Embed. Syst. Lett., 2014

A high performance systolic architecture for k-NN classification.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

An FPGA Implementation of the Hestenes-Jacobi Algorithm for Singular Value Decomposition.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Perf-Sat: Runtime Detection of Performance Saturation for GPGPU Applications.
Proceedings of the 43rd International Conference on Parallel Processing Workshops, 2014

Cache design for mixed criticality real-time systems.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

An Efficient Architecture for Floating-Point Eigenvalue Decomposition.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Towards scalable monitoring and maintenance of rechargeable batteries.
Proceedings of the IEEE International Conference on Electro/Information Technology, 2014

2013
A chaotic encryption scheme for real-time embedded systems: design and implementation.
Telecommun. Syst., 2013

Hardware architectural support for control systems and sensor processing.
ACM Trans. Embed. Comput. Syst., 2013

Securing Multimedia Content Using Joint Compression and Encryption.
IEEE Multim., 2013

A multi-faceted approach to FPGA-based Trojan circuit detection.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Increasing GPU throughput using kernel interleaved thread block scheduling.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms.
Proceedings of the International Conference on Computational Science, 2013

Polarity Trend Analysis of Public Sentiment on YouTube.
Proceedings of the 19th International Conference on Management of Data, 2013

Reduce, Reuse, Recycle (R<sup>3</sup>): A design methodology for Sparse Matrix Vector Multiplication on reconfigurable platforms.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression.
ACM Trans. Embed. Comput. Syst., 2012

An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Improving System Predictability and Performance via Hardware Accelerated Data Structures.
Proceedings of the International Conference on Computational Science, 2012

Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform.
Proceedings of the International Conference on Computational Science, 2012

The secure wavelet transform.
J. Real Time Image Process., 2012

Shepard: A fast exact match short read aligner.
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Design and evaluation of a delay-based FPGA Physically Unclonable Function.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Embedded Multimedia Security Systems - Algorithms and Architectures.
Springer, ISBN: 978-1-4471-4458-8, 2012

2011
Design and Analysis of a Reconfigurable Platform for Frequent Pattern Mining.
IEEE Trans. Parallel Distributed Syst., 2011

A case study in hardware Trojan design and implementation.
Int. J. Inf. Sec., 2011

Efficient mapping and acceleration of AES on custom multi-core architectures.
Concurr. Comput. Pract. Exp., 2011

Teaching graphics processing and architecture using a hardware prototyping approach.
Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

Architectures for Simultaneous Coding and Encryption Using Chaotic Maps.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Using Chaotic Maps for Encrypting Image and Video Content.
Proceedings of the 2011 IEEE International Symposium on Multimedia, 2011

Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
Reconfigurable hardware implementation of a modified chaotic filter bank scheme.
Int. J. Embed. Syst., 2010

Preventing IC Piracy Using Reconfigurable Logic Barriers.
IEEE Des. Test Comput., 2010

A Reconfigurable Architecture for Secure Multimedia Delivery.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A hardware pipeline for accelerating ray traversal algorithms on streaming processors.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

CANSCID-CUDA.
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

Detecting/preventing information leakage on the memory bus due to malicious hardware.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Demonstrable differential power analysis attacks on real-world FPGA-based embedded systems.
Integr. Comput. Aided Eng., 2009

Providing secure execution environments with a last line of defense against Trojan circuit attacks.
Comput. Secur., 2009

Design and Evaluation of a Hardware Accelerated Ray Tracing Data Structure.
Proceedings of the EG UK Theory and Practice of Computer Graphics, 2009

An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet Transform.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Architectural Support for Automated Software Attack Detection, Recovery, and Prevention.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

Efficient Translation of Algorithmic Kernels on Large-Scale Multi-cores.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

Hardware Containers for Software Components: A Trusted Platform for COTS-Based Systems.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

Hardware-enforced fine-grained isolation of untrusted code.
Proceedings of the First ACM Workshop on Secure Execution of Untrusted Code, 2009

2008
An FPGA-Based Network Intrusion Detection Architecture.
IEEE Trans. Inf. Forensics Secur., 2008

Automated software attack recovery using rollback and huddle.
Des. Autom. Embed. Syst., 2008

A Reconfigurable Platform for Frequent Pattern Mining.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Evaluating the effects of cache redundancy on profit.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Mining Association Rules with systolic trees.
Proceedings of the FPL 2008, 2008

Polymorphic wavelet architectures using reconfigurable hardware.
Proceedings of the FPL 2008, 2008

Experiments in attacking FPGA-based embedded systems using differential power analysis.
Proceedings of the 2008 IEEE International Conference on Electro/Information Technology, 2008

Design and analysis of efficient reconfigurable wavelet filters.
Proceedings of the 2008 IEEE International Conference on Electro/Information Technology, 2008

An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Microarchitectures for Managing Chip Revenues under Process Variations.
IEEE Comput. Archit. Lett., 2007

Quantization Error and Accuracy-Performance Tradeoffs for Embedded Data Mining Workloads.
Proceedings of the Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27, 2007

Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Interactive presentation: An FPGA implementation of decision tree classification.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
High-Performance Software Protection Using Reconfigurable Architectures.
Proc. IEEE, 2006

An Architectural Characterization Study of Data Mining and Bioinformatics Workloads.
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

MineBench: A Benchmark Suite for Data Mining Workloads.
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

2005
SAFE-OPS: An approach to embedded software security.
ACM Trans. Embed. Comput. Syst., 2005

Performance Study of a Compiler/Hardware Approach to Embedded Systems Security.
Proceedings of the Intelligence and Security Informatics, 2005

CODESSEAL: Compiler/FPGA Approach to Secure Applications.
Proceedings of the Intelligence and Security Informatics, 2005

Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation.
Proceedings of the Field Programmable Logic and Application, 2004

Design and Evaluation of an FPGA Architecture for Software Protection.
Proceedings of the Field Programmable Logic and Application, 2004

Flow Monitoring in High-Speed Networks with 2D Hash Tables.
Proceedings of the Field Programmable Logic and Application, 2004

Addressing application integrity attacks using a reconfigurable architecture.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Flexible Software Protection Using Hardware/Software Codesign Techniques.
Proceedings of the 2004 Design, 2004

2002
Enhancing Compiler Techniques for Memory Energy Optimizations.
Proceedings of the Embedded Software, Second International Conference, 2002

Optimizing inter-nest data locality.
Proceedings of the International Conference on Compilers, 2002


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