Kees A. Vissers

According to our database, Kees A. Vissers authored at least 74 papers between 1991 and 2022.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2022

FPGA HLS Today: Successes, Challenges, and Opportunities.

Jason Cong, Jason Lau, Gai Liu, Stephen Neuendorffer, Peichen Pan, Kees A. Vissers, Zhiru Zhang

ACM Trans. Reconfigurable Technol. Syst., 2022

Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning.

Tobias Alonso, Lucian Petrica, Mario Ruiz, Jakoba Petri-Koenig, Yaman Umuroglu, Ioannis Stamelos, Elias Koromilas, Michaela Blott, Kees A. Vissers

ACM Trans. Reconfigurable Technol. Syst., 2022

EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators.

Lois Orosa, Skanda Koppula, Yaman Umuroglu, Konstantinos Kanellopoulos, Juan Gómez-Luna, Michaela Blott, Kees A. Vissers, Onur Mutlu

CoRR, 2022

2021

Benchmarking vision kernels and neural network inference accelerators on embedded platforms.

Murad Qasaimeh, Kristof Denolf, Alireza Khodamoradi, Michaela Blott, Jack Lo, Lisa Halder, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones

J. Syst. Archit., 2021

ASLR: An Adaptive Scheduler for Learning Rate.

Alireza Khodamoradi, Kristof Denolf, Kees A. Vissers, Ryan Kastner

Proceedings of the International Joint Conference on Neural Networks, 2021

Trainable Preprocessing for Reduced Precision Neural Networks.

Gábor Csordás, Kristof Denolf, Nicholas J. Fraser, Alessandro Pappalardo, Kees A. Vissers

Proceedings of the 29th European Signal Processing Conference, 2021

2020

FAT: Training Neural Networks for Reliable Inference Under Hardware Faults.

Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers

Proceedings of the IEEE International Test Conference, 2020

Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine.

Prasanth Chatarasi, Stephen Neuendorffer, Samuel Bayliss, Kees A. Vissers, Vivek Sarkar

Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2019

Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs.

Sean Fox, Julian Faraone, David Boland, Kees A. Vissers, Philip H. W. Leong

Proceedings of the International Conference on Field-Programmable Technology, 2019

Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels.

Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones

Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs.

Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP).

Kees A. Vissers

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms.

Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Efficient Error-Tolerant Quantized Neural Network Accelerators.

Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018

FINN-<i>R</i>: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks.

Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser, Kees A. Vissers

ACM Trans. Reconfigurable Technol. Syst., 2018

Keynote 2: Versal: The new Xilinx Adaptive Compute Acceleration Platforms (ACAP).

Kees A. Vissers

Proceedings of the 8th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, 2018

Novel Neural Network Applications on New Python Enabled Platforms.

Kees A. Vissers

Proceedings of the International Conference on Field-Programmable Technology, 2018

2017

Scaling Binarized Neural Networks on Reconfigurable Logic.

Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers

Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017

FINN: A Framework for Fast, Scalable Binarized Neural Network Inference.

Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2015

A Hash Table for Line-Rate Data Processing.

Zsolt István, Gustavo Alonso, Michaela Blott, Kees A. Vissers

ACM Trans. Reconfigurable Technol. Syst., 2015

Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC.

Daniel Jiménez-González, Carlos Álvarez, Antonio Filgueras, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers

CoRR, 2015

Scaling Out to a Single-Node 80Gbps Memcached Server with 40Terabytes of Memory.

Michaela Blott, Ling Liu, Kimon Karras, Kees A. Vissers

Proceedings of the 7th USENIX Workshop on Hot Topics in Storage and File Systems, 2015

Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware.

David Sidler, Gustavo Alonso, Michaela Blott, Kimon Karras, Kees A. Vissers, Raymond Carley

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014

High-Level Synthesis Case Study: Implementation of a Memcached Server.

Kimon Karras, Michaela Blott, Kees A. Vissers

CoRR, 2014

OmpSs@Zynq all-programmable SoC ecosystem.

Antonio Filgueras, Eduard Gil, Daniel Jiménez-González, Carlos Álvarez, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013

Software-programmable digital pre-distortion on the Zynq SoC.

Baris Özgül, Jan Langer, Juanjo Noguera, Kees A. Vissers

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Achieving 10Gbps Line-rate Key-value Stores with FPGAs.

Michaela Blott, Kimon Karras, Ling Liu, Kees A. Vissers, Jeremia Bär, Zsolt István

Proceedings of the 5th USENIX Workshop on Hot Topics in Cloud Computing, 2013

Dataflow architectures for 10Gbps line-rate key-value-stores.

Michaela Blott, Kees A. Vissers

Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

A flexible hash table design for 10GBPS key-value stores on FPGAS.

Zsolt István, Gustavo Alonso, Michaela Blott, Kees A. Vissers

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Reconfigurable computing in the era of post-silicon scaling [panel discussion].

Eric S. Chung, Doug Burger, Mike Butts, Jan Gray, Chuck Thacker, Kees A. Vissers, John Wawrzynek

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012

A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT).

John W. Lockwood, Adwait Gupte, Nishit Mehta, Michaela Blott, Tom English, Kees A. Vissers

Proceedings of the IEEE 20th Annual Symposium on High-Performance Interconnects, 2012

2011

High-Level Synthesis for FPGAs: From Prototyping to Deployment.

Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only).

Sven van Haastregt, Stephen Neuendorffer, Kees A. Vissers, Bart Kienhuis

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools.

Kees A. Vissers, Stephen Neuendorffer, Juanjo Noguera

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Programming high performance signal processing systems in high level languages.

Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009

Using C-to-gates to program streaming image processing kernels efficiently on FPGAs.

Kristof Denolf, Stephen Neuendorffer, Kees A. Vissers

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

The wild west: conquest of complex hardware-dependent software design.

Hiroyuki Yagi, Wolfgang Rosenstiel, Jakob Engblom, Jason Andrews, Kees A. Vissers, Marc Serughetti

Proceedings of the 46th Design Automation Conference, 2009

2008

Streaming Systems in FPGAs.

Stephen Neuendorffer, Kees A. Vissers

Proceedings of the Embedded Computer Systems: Architectures, 2008

2007

A Systematic Approach to Design Low-Power Video Codec Cores.

Kristof Denolf, Adrian Chirila-Rus, Paul R. Schumacher, Robert D. Turney, Kees A. Vissers, Diederik Verkest, Henk Corporaal

EURASIP J. Embed. Syst., 2007

2006

The next generation 65-nm FPGA.

Steve Douglass, Kees A. Vissers, Peter Alfke

Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

2005

IEEE-Compliant IDCT on FPGA-Augmented TriMedia.

Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers

J. VLSI Signal Process., 2005

Communication Primitives Driven Hardware Design and Test Methodology Applied on Complex Video Applications.

Adrian Chirila-Rus, Kristof Denolf, Bart Vanhoof, Paul R. Schumacher, Kees A. Vissers

Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

A scalable, multi-stream MPEG-4 video decoder for conferencing and surveillance applications.

Paul R. Schumacher, Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Nick Fedele, Kees A. Vissers, Jan Bormans

Proceedings of the 2005 International Conference on Image Processing, 2005

Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs.

Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Paul R. Schumacher, Kees A. Vissers

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only).

Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Optimized Generation of Data-Path from C Codes for FPGAs.

Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers

Proceedings of the 2005 Design, 2005

2004

Pel reconstruction on FPGA-augmented TriMedia.

Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers

IEEE Trans. Very Large Scale Integr. Syst., 2004

Programming Extremely Flexible Platforms.

Kees A. Vissers

Proceedings of the Computer Systems: Architectures, 2004

A quantitative analysis of the speedup factors of FPGAs over processors.

Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Programming models and architectures for FPGA platforms.

Kees A. Vissers

Proceedings of the 2004 International Conference on Compilers, 2004

2003

Parallel Processing Architectures for Reconfigurable Systems.

Kees A. Vissers

Proceedings of the 2003 Design, 2003

Panel Title: Reconfigurable Computing - Different Perspectives.

Wolfgang Rosenstiel, Rudy Lauwereins, Ivo Bolsens, Chris Rowen, Yankin Tanurhan, Kees A. Vissers, S. Wang

Proceedings of the 2003 Design, 2003

The future of system-level design: can we find the right solutions to the right problems at the right time?

Reinaldo A. Bergamaschi, Grant Martin, Wayne H. Wolf, Rolf Ernst, Kees A. Vissers, Jack Kouloheris

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002

Developing Architectural Platforms: A Disciplined Approach.

Andrew Mihal, Chidamber Kulkarni, Matthew W. Moskewicz, Mel M. Tsai, Niraj Shah, Scott J. Weber, Yujia Jin, Kurt Keutzer, Christian Sauer, Kees A. Vissers, Sharad Malik

IEEE Des. Test Comput., 2002

A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study.

Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers

Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach.

Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers

Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Field-Programmable Custom Computing Machines - A Taxonomy -.

Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers

Proceedings of the Field-Programmable Logic and Applications, 2002

MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64.

Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001

A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems.

Paul Lieverse, Pieter van der Wolf, Kees A. Vissers, Ed F. Deprettere

J. VLSI Signal Process., 2001

MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor.

Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia.

Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers

Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000

The Future of Flexible HW Platform Architectures Panel Discussion.

Rolf Ernst, Grant Martin, Oz Levia, Pierre G. Paulin, Stamatis Vassiliadis, Kees A. Vissers

Proceedings of the 2000 Design, 2000

YAPI: application modeling for signal processing systems.

Erwin A. de Kock, W. J. M. Smits, Pieter van der Wolf, Jean-Yves Brunel, W. M. Kruijtzer, Paul Lieverse, Kees A. Vissers, Gerben Essink

Proceedings of the 37th Conference on Design Automation, 2000

1999

TriMedia CPU64 Application Domain and Benchmark Suite.

A. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans

Proceedings of the IEEE International Conference On Computer Design, 1999

TriMedia CPU64 Architecture.

Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel

Proceedings of the IEEE International Conference On Computer Design, 1999

System level design and debug of high-performance embedded media systems (tutorial).

Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

An MPEG-2 decoder case study as a driver for a system level design methodology.

Pieter van der Wolf, Paul Lieverse, Mudit Goel, David La Hei, Kees A. Vissers

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998

Design space exploration for future TriMedia CPUs.

Frans Sijstermans, Evert-Jan D. Pol, Bram Riemens, Kees A. Vissers, Selliah Rathnam, Gert Slavenburg

Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

The construction of a retargetable simulator for an architecture template.

Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf

Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997

Trade-offs in the design of mixed hardware-software systems-a perspective from industry.

Kees A. Vissers

Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures.

Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1995

Architecture and programming of two generations video signal processors.

Kees A. Vissers, Gerben Essink, Piet J. van Gerwen, P. J. M. Janssen, O. Popp, E. Riddersma, W. J. M. Smits, Harry J. M. Veendrick

Microprocess. Microprogramming, 1995

1991

Architecture and Programming of a VLIW Style Programmable Video Signal Processor.

Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers

Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

Scheduling in Programmable Video Signal Processors.

Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991