Kees A. Vissers

According to our database1, Kees A. Vissers authored at least 68 papers between 1991 and 2019.

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Bibliography

2019
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels.
CoRR, 2019

Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP).
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks.
TRETS, 2018

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs.
CoRR, 2018

Keynote 2: Versal: The new Xilinx Adaptive Compute Acceleration Platforms (ACAP).
Proceedings of the 8th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, 2018

Novel Neural Network Applications on New Python Enabled Platforms.
Proceedings of the International Conference on Field-Programmable Technology, 2018

2017
Scaling Binarized Neural Networks on Reconfigurable Logic.
CoRR, 2017

Scaling Binarized Neural Networks on Reconfigurable Logic.
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017

FINN: A Framework for Fast, Scalable Binarized Neural Network Inference.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference.
CoRR, 2016

2015
A Hash Table for Line-Rate Data Processing.
TRETS, 2015

Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC.
CoRR, 2015

Scaling Out to a Single-Node 80Gbps Memcached Server with 40Terabytes of Memory.
Proceedings of the 7th USENIX Workshop on Hot Topics in Storage and File Systems, 2015

Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
High-Level Synthesis Case Study: Implementation of a Memcached Server.
CoRR, 2014

OmpSs@Zynq all-programmable SoC ecosystem.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Software-programmable digital pre-distortion on the Zynq SoC.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Achieving 10Gbps Line-rate Key-value Stores with FPGAs.
Proceedings of the 5th USENIX Workshop on Hot Topics in Cloud Computing, 2013

Dataflow architectures for 10Gbps line-rate key-value-stores.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

A flexible hash table design for 10GBPS key-value stores on FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Reconfigurable computing in the era of post-silicon scaling [panel discussion].
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT).
Proceedings of the IEEE 20th Annual Symposium on High-Performance Interconnects, 2012

2011
High-Level Synthesis for FPGAs: From Prototyping to Deployment.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Programming high performance signal processing systems in high level languages.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009
Using C-to-gates to program streaming image processing kernels efficiently on FPGAs.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

The wild west: conquest of complex hardware-dependent software design.
Proceedings of the 46th Design Automation Conference, 2009

2008
Streaming Systems in FPGAs.
Proceedings of the Embedded Computer Systems: Architectures, 2008

2007
A Systematic Approach to Design Low-Power Video Codec Cores.
EURASIP J. Emb. Sys., 2007

Optimized Generation of Data-Path from C Codes for FPGAs
CoRR, 2007

2005
IEEE-Compliant IDCT on FPGA-Augmented TriMedia.
VLSI Signal Processing, 2005

Communication Primitives Driven Hardware Design and Test Methodology Applied on Complex Video Applications.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

A scalable, multi-stream MPEG-4 video decoder for conferencing and surveillance applications.
Proceedings of the 2005 International Conference on Image Processing, 2005

Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Optimized Generation of Data-Path from C Codes for FPGAs.
Proceedings of the 2005 Design, 2005

2004
Pel reconstruction on FPGA-augmented TriMedia.
IEEE Trans. VLSI Syst., 2004

Programming Extremely Flexible Platforms.
Proceedings of the Computer Systems: Architectures, 2004

A quantitative analysis of the speedup factors of FPGAs over processors.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Programming models and architectures for FPGA platforms.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
Parallel Processing Architectures for Reconfigurable Systems.
Proceedings of the 2003 Design, 2003

Panel Title: Reconfigurable Computing - Different Perspectives.
Proceedings of the 2003 Design, 2003

The future of system-level design: can we find the right solutions to the right problems at the right time?
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Developing Architectural Platforms: A Disciplined Approach.
IEEE Design & Test of Computers, 2002

A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Field-Programmable Custom Computing Machines - A Taxonomy -.
Proceedings of the Field-Programmable Logic and Applications, 2002

MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001
A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems.
VLSI Signal Processing, 2001

MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000
The Future of Flexible HW Platform Architectures Panel Discussion.
Proceedings of the 2000 Design, 2000

YAPI: application modeling for signal processing systems.
Proceedings of the 37th Conference on Design Automation, 2000

1999
TriMedia CPU64 Application Domain and Benchmark Suite.
Proceedings of the IEEE International Conference On Computer Design, 1999

TriMedia CPU64 Architecture.
Proceedings of the IEEE International Conference On Computer Design, 1999

System level design and debug of high-performance embedded media systems (tutorial).
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

An MPEG-2 decoder case study as a driver for a system level design methodology.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Design space exploration for future TriMedia CPUs.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

The construction of a retargetable simulator for an architecture template.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997
Trade-offs in the design of mixed hardware-software systems-a perspective from industry.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1995
Architecture and programming of two generations video signal processors.
Microprocessing and Microprogramming, 1995

1991
Architecture and Programming of a VLIW Style Programmable Video Signal Processor.
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

Scheduling in Programmable Video Signal Processors.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991


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