Pilar Parra Fernández

According to our database, Pilar Parra Fernández authored at least 12 papers between 2002 and 2020.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2020

Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA.

Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero, Carmen Baena Oliva, Pilar Parra Fernández, Carlos Jesús Jiménez-Fernández

Sensors, 2020

An Academic Approach to FPGA Design Based on a Distance Meter Circuit.

Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero

Rev. Iberoam. de Tecnol. del Aprendiz., 2020

2018

Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher.

Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Manuel Valencia-Barrero

Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2010

Optimization of clock-gating structures for low-leakage high-performance applications.

Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures.

Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2007

Asymmetric clock driver for improved power and noise performances.

Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A switching noise vision of the optimization techniques for low-power synthesis.

Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

Optimization of Master-Slave Flip-Flops for High-Performance Applications.

Raúl Jiménez, Pilar Parra Fernández, Javier Castro-Ramirez, Manuel Sanchez-Raya, Antonio J. Acosta

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2005

Selective Clock-Gating for Low-Power Synchronous Counters.

Pilar Parra Fernández, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia-Barrero

J. Low Power Electron., 2005

2003

A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application.

Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta

Proceedings of the Integrated Circuit and System Design, 2003

2002

Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1.

Pilar Parra Fernández, Antonio J. Acosta, Manuel Valencia-Barrero

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches.

Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002