Raúl Jiménez

Orcid: 0000-0002-8125-1586

According to our database1, Raúl Jiménez authored at least 27 papers between 1995 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
Gravitational Duals from Equations of State.
CoRR, 2024

2023
Depth-based reconstruction method for incomplete functional data.
Comput. Stat., September, 2023

Localization processes for functional data analysis.
Adv. Data Anal. Classif., June, 2023

Integrated Depths for Partially Observed Functional Data.
J. Comput. Graph. Stat., April, 2023

2022
On projection methods for functional time series forecasting.
J. Multivar. Anal., 2022

2017
A Wireless Sensor System for Real-Time Monitoring and Fault Detection of Motor Arrays.
Sensors, 2017

2015
Touch OK to Continue: Error Messages and Affective Response on Interactive Public Displays.
Proceedings of the 4th International Symposium on Pervasive Displays, 2015

2014
Low voltage analog readout channel based on gain-boosted amplifiers.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

2013
Distributed Peer Discovery in Large-Scale P2P Streaming Systems : Addressing Practical Problems of P2P Deployments on the Open Internet.
PhD thesis, 2013

ROS Methodology to Work with Non-ROS Mobile Robots: Experimental Uses in Mobile Robotics Teaching.
Proceedings of the ROBOT 2013: First Iberian Robotics Conference, 2013

FPGA-based implementation of a real-time timing measuring device.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
VLSI Implementation of digital frequency sensors as hardware countermeasure.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Sub-second lookups on a large-scale Kademlia-based overlay.
Proceedings of the 2011 IEEE International Conference on Peer-to-Peer Computing, 2011

2010
A compact voltage-controlled transconductor with high linearity.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Connectivity Properties of Mainline BitTorrent DHT Nodes.
Proceedings of the Proceedings P2P 2009, 2009

2006
Bounded-rational-prisoners' dilemma: On critical phenomena of cooperation.
Appl. Math. Comput., 2006

Optimization of Master-Slave Flip-Flops for High-Performance Applications.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2005
Selective Clock-Gating for Low-Power Synchronous Counters.
J. Low Power Electron., 2005

Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms.
Proceedings of the Integrated Circuit and System Design, 2005

2003
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application.
Proceedings of the Integrated Circuit and System Design, 2003

2002
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001
Low-power logic styles for full-adder circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Practical low-cost CPL implementations threshold logic functions.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits.
Proceedings of the Integrated Circuit Design, 2000

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.
Proceedings of the Integrated Circuit Design, 2000

1998
Efficient self-timed circuits based on weak NMOS-trees.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1995
New CMOS VLSI linear self-timed architectures.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995


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