Manuel Valencia-Barrero

According to our database, Manuel Valencia-Barrero authored at least 31 papers between 1986 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations.

Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández

Sensors, 2021

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA.

Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández

IEEE Access, 2021

2020

ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium.

José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

IEEE Trans. Circuits Syst., 2020

Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA.

Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero, Carmen Baena Oliva, Pilar Parra Fernández, Carlos Jesús Jiménez-Fernández

Sensors, 2020

An Academic Approach to FPGA Design Based on a Distance Meter Circuit.

Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero

Rev. Iberoam. de Tecnol. del Aprendiz., 2020

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers.

Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Ricardo Chaves, Manuel Valencia-Barrero, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018

Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher.

Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Manuel Valencia-Barrero

Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017

Vulnerability Analysis of Trivium FPGA Implementations.

Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

IEEE Trans. Very Large Scale Integr. Syst., 2017

Multiradix Trivium Implementations for Low-Power IoT Hardware.

José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

IEEE Trans. Very Large Scale Integr. Syst., 2017

Trivium hardware implementations for power reduction.

José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

Int. J. Circuit Theory Appl., 2017

2016

Fault attack on FPGA implementations of Trivium stream cipher.

Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2012

Low Power Implementation of Trivium Stream Cipher.

José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

2008

Logic Synthesis.

Angel Barriga, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

2007

Asymmetric clock driver for improved power and noise performances.

Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A switching noise vision of the optimization techniques for low-power synthesis.

Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2005

Selective Clock-Gating for Low-Power Synchronous Counters.

Pilar Parra Fernández, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia-Barrero

J. Low Power Electron., 2005

2002

Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1.

Pilar Parra Fernández, Antonio J. Acosta, Manuel Valencia-Barrero

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.

Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001

Gate-level simulation of CMOS circuits using the IDDM model.

Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

AUTODDM: automatic characterization tool for the delay degradation model.

Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carmen Baena Oliva, Manuel Valencia

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model.

Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Degradation Delay Model Extension to CMOS Gates.

Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero

Proceedings of the Integrated Circuit Design, 2000

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.

Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero

Proceedings of the Integrated Circuit Design, 2000

Inertial and degradation delay model for CMOS logic gates.

Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998

Efficient self-timed circuits based on weak NMOS-trees.

Raúl Jiménez, Antonio J. Acosta, Angel Barriga, Manuel J. Bellido, Manuel Valencia

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1995

SODS: a new CMOS differential-type structure.

Antonio J. Acosta, Manuel Valencia, Angel Barriga, Manuel J. Bellido, José L. Huertas

IEEE J. Solid State Circuits, July, 1995

Modular Asynchronous Arbiter Insensitive to Metastability.

Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano

IEEE Trans. Computers, 1995

New CMOS VLSI linear self-timed architectures.

Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas

Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1993

A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch.

Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Modeling of real bistables in VHDL.

Antonio J. Acosta, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas

Proceedings of the European Design Automation Conference 1993, 1993

1986

Asynchronous Modular Arbiter.

J. Calvo, José I. Acha, Manuel Valencia-Barrero

IEEE Trans. Computers, 1986