Manuel Valencia-Barrero

Affiliations:
  • Czech Technical University in Prague, Department of Circuit Theory, Czech Republic


According to our database1, Manuel Valencia-Barrero authored at least 27 papers between 1986 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Bibliography

2020
ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium.
IEEE Trans. Circuits Syst., 2020

Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA.
Sensors, 2020

An Academic Approach to FPGA Design Based on a Distance Meter Circuit.
Rev. Iberoam. de Tecnol. del Aprendiz., 2020

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
Vulnerability Analysis of Trivium FPGA Implementations.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Multiradix Trivium Implementations for Low-Power IoT Hardware.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Trivium hardware implementations for power reduction.
Int. J. Circuit Theory Appl., 2017

2016
Fault attack on FPGA implementations of Trivium stream cipher.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2012
Low Power Implementation of Trivium Stream Cipher.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

2008
Logic Synthesis.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

2007
Asymmetric clock driver for improved power and noise performances.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A switching noise vision of the optimization techniques for low-power synthesis.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2005
Selective Clock-Gating for Low-Power Synchronous Counters.
J. Low Power Electron., 2005

2002
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001
Gate-level simulation of CMOS circuits using the IDDM model.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

AUTODDM: automatic characterization tool for the delay degradation model.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Degradation Delay Model Extension to CMOS Gates.
Proceedings of the Integrated Circuit Design, 2000

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.
Proceedings of the Integrated Circuit Design, 2000

1998
Efficient self-timed circuits based on weak NMOS-trees.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1995
Modular Asynchronous Arbiter Insensitive to Metastability.
IEEE Trans. Computers, 1995

New CMOS VLSI linear self-timed architectures.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1993
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Modeling of real bistables in VHDL.
Proceedings of the European Design Automation Conference 1993, 1993

1986
Asynchronous Modular Arbiter.
IEEE Trans. Computers, 1986


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