Ping-Ying Wang

According to our database1, Ping-Ying Wang authored at least 14 papers between 2005 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 1V fractional-N PLL with nonlinearity-insensitive modulator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012
An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

2011
An all-digital built-in self-test technique for transfer function characterization of RF PLLs.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
All digital modulation bandwidth extension technique for narrow bandwidth analog fractional-N PLL.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes.
IEEE J. Solid State Circuits, 2009

2008
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A charge pump-based direct frequency modulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A fractional spur reduction technique for RF TDC-based all digital PLLs.
Proceedings of the ESSCIRC 2008, 2008

An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Chaos in delay locked loop.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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