Hsiang-Hui Chang

According to our database, Hsiang-Hui Chang authored at least 15 papers between 2002 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM.

Tzung-Han Wu, Hsiang-Hui Chang, Shin-Fu Chen, Chinq-Shiun Chiu, Li-Shin Lai, Chi-Hsueh Wang, Song-Yu Yang, Ta-Hsin Lin, Jhy-Rong Chen, Hung-Chieh Tsai, Chi-Yao Yu, Sheng-Yuan Su, Tai-Yuan Yu, Chieh-Chuan Chin, Guang-Kaai Dehng, Augusto Marques, Caiyi Wang, George Chien

IEEE J. Solid State Circuits, 2013

2011

A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC.

Chi-Yao Yu, Ivan Siu-Chuang Lu, Yen-Horng Chen, Lan-chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, Hsiang-Hui Chang, Wen-Chang Lee, Sheng-Jui Huang, Tzung-Han Wu, Chinq-Shiun Chiu, George Chien

IEEE J. Solid State Circuits, 2011

A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS.

Lan-Chou Cho, Hsiang-Hui Chang, Augusto Marques, Albert Yang, Chinq-Shiun Chiu, Guang-Kaai Dehng

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2009

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes.

Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Hsiu-Ming (Sherman) Chang

IEEE J. Solid State Circuits, 2009

2008

A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE.

Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A fractional spur reduction technique for RF TDC-based all digital PLLs.

Ping-Ying Wang, Hsiang-Hui Chang, Jing-Hong Conan Zhan

Proceedings of the ESSCIRC 2008, 2008

An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability.

Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Bing-Yu Hsieh

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2006

A 0.7-2-GHz self-calibrated multiphase delay-locked loop.

Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2006

2005

A wide-range and fast-locking all-digital cycle-controlled delay-locked loop.

Hsiang-Hui Chang, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2005

2004

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection.

Hsiang-Hui Chang, Rong-Jyi Yang, Shen-Iuan Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

2003

A fast locking and low jitter delay-locked loop using DHDL.

Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2003

A spread-spectrum clock generator with triangular modulation.

Hsiang-Hui Chang, I-Hui Hua, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2003

A shifted-averaging VCO with precise multiphase outputs and low jitter operation.

Hsiang-Hui Chang, Shang-Ping Chen, Shen-Iuan Liu

Proceedings of the ESSCIRC 2003, 2003

2002

A wide-range delay-locked loop with a fixed latency of one clock cycle.

Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2002

A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay.

Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002