Po-Hsuan Chang

Orcid: 0000-0002-2232-3738

According to our database1, Po-Hsuan Chang authored at least 6 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2023
A Sub-500fJ/bit 3D Direct Bond Silicon Photonic Transceiver in 12nm FinFET.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Direct Bond Interconnect 3D Co-Integrated Silicon-Photonic Transceiver in 12nm FinFET with -20.3dBm OMA Sensitivity and 691fJ/bit.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

2022
A 12.5 Gb/s 1.38 mW Inverter-Based Optical Receiver in 28 nm CMOS.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

2020
A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2014
A 10Gb/s 44.2 dB adaptive equalizer with Duobinary tracking loop in 0.18µm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A 6Gb/s 40dB burst-mode digitally adaptive equalizer with reference-calibrated overshoot control.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013


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