Sebastian Hoyos
Orcid: 0000-0002-2691-3700
According to our database1,
Sebastian Hoyos
authored at least 67 papers
between 2004 and 2024.
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Bibliography
2024
IEEE Trans. Mob. Comput., April, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
Guest Editorial Special Issue on the 2023 IEEE International Symposium on Circuits and Systems.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023
A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET.
IEEE J. Solid State Circuits, March, 2023
A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET.
IEEE J. Solid State Circuits, 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
Multi-Channel Receiver Nonlinearity Cancellation Using Channel Speculation Passing Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2020
Kalman-Based Real-Time Functional Decomposition for the Spectral Calibration in Swept Source Optical Coherence Tomography.
IEEE Trans. Biomed. Circuits Syst., 2020
A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture : (Invited Special Session Paper).
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
2018
A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
The Spectral Calibration of Swept-Source Optical Coherence Tomography Systems Using Unscented Kalman Filter.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017
Towards an on-chip signal processing solution for the online calibration of SS-OCT systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 14th IEEE International Symposium on Biomedical Imaging, 2017
2016
A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization.
IEEE J. Solid State Circuits, 2016
A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS.
IEEE J. Solid State Circuits, 2016
IEEE Commun. Mag., 2016
Compressed Power Spectral Density Estimation via Group-Based Total Variation Minimization.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the Symposium on VLSI Circuits, 2015
3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications.
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014
2013
IEEE J. Solid State Circuits, 2013
Proceedings of the IEEE 9th International Conference on Mobile Ad-hoc and Sensor Networks, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
2012
A 15 MHz to 600 MHz, 20 mW, 0.38 mm<sup>2</sup> Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Sensitivity Analysis of Continuous-Time Δ Σ ADCs to Out-of-Band Blockers in Future SAW-Less Multi-Standard Wireless Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
The impact of ADC nonlinearity in a mixed-signal compressive sensing system for frequency-domain sparse signals.
Phys. Commun., 2012
J. Circuits Syst. Comput., 2012
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Corrections to "A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing".
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Analytical framework and bandwidth optimisation of orthogonal frequency division multiplexing low-order multi-channel filter-bank receivers for achieving sampling clock-jitter robustness.
IET Circuits Devices Syst., 2011
Sensitivity analysis of pulse-width jitter induced noise in continuous-time delta-sigma modulators to out-of-band blockers in wireless receivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
A Multiphase Multipath Technique With Digital Phase Shifters for Harmonic Distortion Cancellation.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth.
IEEE J. Solid State Circuits, 2010
Int. J. Digit. Multim. Broadcast., 2010
2009
Proceedings of the IEEE International Conference on Systems, 2009
A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
Proceedings of the IEEE International Conference on Acoustics, 2008
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE Trans. Wirel. Commun., 2007
2006
Broadband multicarrier communication receiver based on analog to digital conversion in the frequency domain.
IEEE Trans. Wirel. Commun., 2006
2005
IEEE Trans. Wirel. Commun., 2005
IEEE Trans. Veh. Technol., 2005
IEEE Trans. Signal Process., 2005
Ultra-wideband multicarrier communication receiver based on analog to digital conversion in the frequency domain.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2005
2004
IEEE Trans. Signal Process., 2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
High-speed A/D conversion for ultra-wideband signals based on signal projection over basis functions.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004