According to our database1, Il-Min Yi authored at least 11 papers between 2012 and 2018.
Legend:Book In proceedings Article PhD thesis Other
A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface.
IEEE J. Solid State Circuits, 2018
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2016
A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2014
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2014
A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines.
IEEE J. Solid State Circuits, 2012
An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits.
Proceedings of the International SoC Design Conference, 2012