Prasanth Mangalagiri

According to our database1, Prasanth Mangalagiri authored at least 11 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2019
Analog Layout Synthesis: Are We There Yet?
Proceedings of the 2019 International Symposium on Physical Design, 2019

2009
An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization.
IEEE Trans. Computers, 2009

Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Exploiting clock skew scheduling for FPGA.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Toward Increasing FPGA Lifetime.
IEEE Trans. Dependable Secur. Comput., 2008

Thermal-aware reliability analysis for platform FPGAs.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A low-power phase change memory based hybrid cache architecture.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

FPGA routing architecture analysis under variations.
Proceedings of the 25th International Conference on Computer Design, 2007

TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms.
Proceedings of the FPL 2007, 2007

2006
FLAW: FPGA lifetime awareness.
Proceedings of the 43rd Design Automation Conference, 2006


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