Kanwaldeep Sobti

According to our database1, Kanwaldeep Sobti authored at least 8 papers between 2006 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
Accurate Area, Time and Power Models for FPGA-Based Implementations.
J. Signal Process. Syst., 2011

Structural tests of slave clock gating in low-power flip-flop.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010
The scan-DFT features of AMD's next-generation microprocessor core.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization.
IEEE Trans. Computers, 2009

2008
Accurate models for estimating area and power of FPGA implementations.
Proceedings of the IEEE International Conference on Acoustics, 2008

2007
Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms.
Proceedings of the FPL 2007, 2007

2006
Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006


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