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Qianjian Xing

Orcid: 0000-0002-5671-6118

Affiliations:
  • Zhejiang University, Hangzhou, China


According to our database1, Qianjian Xing authored at least 11 papers between 2014 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

On csauthors.net:

Bibliography

2021
High-Parallelism Hash-Merge Architecture for Accelerating Join Operation on FPGA.
[BibTeX]
[DOI]
Wen-Qi Wu
,
Meiting Xue
,
Qianjian Xing
,
Feng Yu
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
MFCFSiam: A Correlation-Filter-Guided Siamese Network with Multifeature for Visual Tracking.
[BibTeX]
[DOI]
Chenpu Li
,
Qianjian Xing
,
Zhenguo Ma
,
Ke Zang
Wirel. Commun. Mob. Comput., 2020

FPGA-Accelerated Hash Join Operation for Relational Databases.
[BibTeX]
[DOI]
Meiting Xue
,
Qianjian Xing
,
Chen Feng
,
Feng Yu
,
Zhen-Guo Ma
IEEE Trans. Circuits Syst. II Express Briefs, 2020

HKSiamFC: Visual-Tracking Framework Using Prior Information Provided by Staple and Kalman Filter.
[BibTeX]
[DOI]
Chenpu Li
,
Qianjian Xing
,
Zhenguo Ma
Sensors, 2020

2018
A Fused Continuous Floating-Point MAC on FPGA.
[BibTeX]
[DOI]
Min Yuan
,
Qianjian Xing
,
Zhen-guo Ma
,
Feng Yu
,
Yingke Xu
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

2017
A Novel Conflict-Free Parallel Memory Access Scheme for FFT Processors.
[BibTeX]
[DOI]
Qianjian Xing
,
Zhen-guo Ma
,
Yingke Xu
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Continuous-Flow Memory-Based Architecture for Real-Valued FFT.
[BibTeX]
[DOI]
Xiubin Mao
,
Zhen-guo Ma
,
Feng Yu
,
Qianjian Xing
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture.
[BibTeX]
[DOI]
Qianjian Xing
,
Zhen-guo Ma
,
Feng Yu
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Modular Serial Pipelined Sorting Architecture for Continuous Variable-Length Sequences with a Very Simple Control Strategy.
[BibTeX]
[DOI]
Tingting Chen
,
Weijun Li
,
Feng Yu
,
Qianjian Xing
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2015
Pipelined Architecture for a Radix-2 Fast Walsh-Hadamard-Fourier Transform Algorithm.
[BibTeX]
[DOI]
Jinqi Liu
,
Qianjian Xing
,
Xiaobo Yin
,
Xiubin Mao
,
Feng Yu
IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014
Radix-R WHT-FFT with Identical Stage-to-Stage Interconnection Pattern.
[BibTeX]
[DOI]
Qianjian Xing
,
Feng Yu
,
Xiaobo Yin
,
Bei Zhao
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014


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