Zhen-guo Ma

According to our database, Zhen-guo Ma authored at least 30 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

FedLC: Accelerating Asynchronous Federated Learning in Edge Computing.

Yang Xu, Zhenguo Ma, Hongli Xu, Suo Chen, Jianchun Liu, Yinxing Xue

IEEE Trans. Mob. Comput., May, 2024

Like Attracts Like: Personalized Federated Learning in Decentralized Edge Computing.

Zhenguo Ma, Yang Xu, Hongli Xu, Jianchun Liu, Yinxing Xue

IEEE Trans. Mob. Comput., February, 2024

Optimised Serial Commutator FFT Architecture in Terms of Multiplexers.

Hongji Fang, Zhenguo Ma, Feng Yu, Bei Zhao, Bo Zhang

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023

Adaptive Control of Local Updating and Model Compression for Efficient Federated Learning.

Yang Xu, Yunming Liao, Hongli Xu, Zhenguo Ma, Lun Wang, Jianchun Liu

IEEE Trans. Mob. Comput., October, 2023

Adaptive Batch Size for Federated Learning in Resource-Constrained Edge Computing.

Zhenguo Ma, Yang Xu, Hongli Xu, Zeyu Meng, Liusheng Huang, Yinxing Xue

IEEE Trans. Mob. Comput., 2023

Accelerating Hierarchical Federated Learning with Adaptive Aggregation Frequency in Edge Computing.

Suo Chen, Zhenguo Ma, Zhiyuan Wang

Proceedings of the 2023 4th International Conference on Computing, 2023

2022

Parallel Pipelined Architecture and Algorithm for Matrix Transposition Using Registers.

Bo Zhang, Zhenguo Ma, Wei Luo

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT.

Hongji Fang, Bo Zhang, Feng Yu, Bei Zhao, Zhenguo Ma

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Stream-Based Lossless Compression of Sensor Signals Using an Integer Adaptive Predictor.

Qianhao Chen, Wenqi Wu, Haori Zheng, Bei Zhao, Zhenguo Ma, Weijie Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021

A Novel Pipelined Algorithm and Modular Architecture for Non-Square Matrix Transposition.

Bo Zhang, Zhenguo Ma, Feng Yu

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Communication-efficient asynchronous federated learning in resource-constrained edge computing.

Jianchun Liu, Hongli Xu, Yang Xu, Zhenguo Ma, Zhiyuan Wang, Chen Qian, He Huang

Comput. Networks, 2021

Joint Network Selection and Task Offloading in Mobile Edge Computing.

Xin Qi, Hongli Xu, Zhenguo Ma, Suo Chen

Proceedings of the 21st IEEE/ACM International Symposium on Cluster, 2021

2020

MFCFSiam: A Correlation-Filter-Guided Siamese Network with Multifeature for Visual Tracking.

Chenpu Li, Qianjian Xing, Zhenguo Ma, Ke Zang

Wirel. Commun. Mob. Comput., 2020

FPGA-Accelerated Hash Join Operation for Relational Databases.

Meiting Xue, Qianjian Xing, Chen Feng, Feng Yu, Zhen-Guo Ma

IEEE Trans. Circuits Syst. II Express Briefs, 2020

High-Throughput Parallel SRAM-Based Hash Join Architecture on FPGA.

Wen-Qi Wu, Meiting Xue, Tian-Qi Zhu, Zhen-Guo Ma, Feng Yu

IEEE Trans. Circuits Syst., 2020

HKSiamFC: Visual-Tracking Framework Using Prior Information Provided by Staple and Kalman Filter.

Chenpu Li, Qianjian Xing, Zhenguo Ma

Sensors, 2020

Nonlinear Quality Indices Based on a Novel Lempel-Ziv Complexity for Assessing Quality of Multi-Lead ECGs Collected in Real Time.

Yatao Zhang, Zhenguo Ma, Wentao Dong

J. Inf. Process. Syst., 2020

Automatic Modulation Classification Based on Hierarchical Recurrent Neural Networks With Grouped Auxiliary Memory.

Ke Zang, Zhenguo Ma

IEEE Access, 2020

2019

Resource-Efficient Parallel Tree-Based Join Architecture on FPGA.

Huan Zhang, Bei Zhao, Wei-Jun Li, Zhen-Guo Ma, Feng Yu

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Pipelined Algorithm and Modular Architecture for Matrix Transposition.

Yunxiang Wang, Zhen-guo Ma, Feng Yu

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Comparing Performance of Iterative and Non-Iterative Classifiers for 2-Lead ECGs on Multi-Feature Schemes.

Zhenguo Ma, Bingrui Chen, Yuan Xu, Yangxiao Li, Yatao Zhang

Proceedings of the 12th International Congress on Image and Signal Processing, 2019

2018

A Fused Continuous Floating-Point MAC on FPGA.

Min Yuan, Qianjian Xing, Zhen-guo Ma, Feng Yu, Yingke Xu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

2017

A Novel Conflict-Free Parallel Memory Access Scheme for FFT Processors.

Qianjian Xing, Zhen-guo Ma, Yingke Xu

IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Continuous-Flow Memory-Based Architecture for Real-Valued FFT.

Xiubin Mao, Zhen-guo Ma, Feng Yu, Qianjian Xing

IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture.

Qianjian Xing, Zhen-guo Ma, Feng Yu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016

Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths.

Xiaobo Yin, Feng Yu, Zhen-guo Ma

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Efficient Circuit for Parallel Bit Reversal.

Weijun Li, Feng Yu, Zhen-guo Ma

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Time Delay Estimation via Co-Prime Aliased Sparse FFT.

Bei Zhao, Chen Cheng, Zhen-guo Ma, Feng Yu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2015

A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm.

Zhen-guo Ma, Xiaobo Yin, Feng Yu

IEEE Trans. Circuits Syst. II Express Briefs, 2015

2011

An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays.

Zhen-guo Ma, Feng Yu, Rui-feng Ge, Ze-ke Wang

J. Zhejiang Univ. Sci. C, 2011