Feng Yu

Orcid: 0000-0002-9740-2537

Affiliations:

Zhejiang University, College of Biomedical Engineering and Instrument Science, Hangzhou, China
Zhejiang University, Department of Instrument Engineering, Hangzhou, China (PhD 2007)

According to our database¹, Feng Yu authored at least 43 papers between 2011 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

Dataset

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Bibliography

2024

Optimised Serial Commutator FFT Architecture in Terms of Multiplexers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023

General Adaptive Lossless Compression for Multi-Channel Sensor Signals.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, December, 2023

DTP-Net: Learning to Reconstruct EEG signals in Time-Frequency Domain by Multi-scale Feature Reuse.

[BibT_eX]

[DOI]

CoRR, 2023

2022

Resource Efficient Top-<i>K</i> Sorter on FPGA.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., September, 2022

A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021

A Novel Pipelined Algorithm and Modular Architecture for Non-Square Matrix Transposition.

[BibT_eX]

[DOI]

Bo Zhang

Zhenguo Ma

Feng Yu

IEEE Trans. Circuits Syst. II Express Briefs, 2021

High-Parallelism Hash-Merge Architecture for Accelerating Join Operation on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020

FPGA-Accelerated Hash Join Operation for Relational Databases.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

High-Throughput Parallel SRAM-Based Hash Join Architecture on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Modular Pipeline Architecture for Accelerating Join Operation in RDBMS.

[BibT_eX]

[DOI]

Weijie Chen

Weijun Li

Feng Yu

IEEE Trans. Circuits Syst., 2020

A Hybrid Pipelined Architecture for High Performance Top-K Sorting on FPGA.

[BibT_eX]

[DOI]

Weijie Chen

Weijun Li

Feng Yu

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Multi-Branch Convolutional Neural Network for Automatic Sleep Stage Classification with Embedded Stage Refinement and Residual Attention Channel Fusion.

[BibT_eX]

[DOI]

Tianqi Zhu

Wei Luo

Feng Yu

Sensors, 2020

Learning longer-term dependencies via grouped distributor unit.

[BibT_eX]

[DOI]

Wei Luo

Feng Yu

Neurocomputing, 2020

Sorting Matrix Architecture for Continuous Data Sequences.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

2019

Resource-Efficient Parallel Tree-Based Join Architecture on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Pipelined Algorithm and Modular Architecture for Matrix Transposition.

[BibT_eX]

[DOI]

Yunxiang Wang

Zhen-guo Ma

Feng Yu

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Recurrent Highway Networks With Grouped Auxiliary Memory.

[BibT_eX]

[DOI]

Wei Luo

Feng Yu

IEEE Access, 2019

Fast and Robust Diffusion Kurtosis Parametric Mapping Using a Three-Dimensional Convolutional Neural Network.

[BibT_eX]

[DOI]

IEEE Access, 2019

2018

A Fused Continuous Floating-Point MAC on FPGA.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

2017

A Continuous-Flow Memory-Based Architecture for Real-Valued FFT.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Parameterized L1-Minimization Algorithm for Off-the-Gird Spectral Compressive Sensing.

[BibT_eX]

[DOI]

Wei Zhang

Feng Yu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture.

[BibT_eX]

[DOI]

Qianjian Xing

Zhen-guo Ma

Feng Yu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Modular Serial Pipelined Sorting Architecture for Continuous Variable-Length Sequences with a Very Simple Control Strategy.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Dynamic Parameterized $\ell _{1}$ -Regulation for Single-Snapshot DOA Estimations.

[BibT_eX]

[DOI]

Wei Zhang

Feng Yu

IEEE Commun. Lett., 2017

Off-the-Grid Compressive Time Delay Estimation via Manifold-Based Optimization.

[BibT_eX]

[DOI]

Wei Zhang

Feng Yu

IEEE Commun. Lett., 2017

2016

Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths.

[BibT_eX]

[DOI]

Xiaobo Yin

Feng Yu

Zhen-guo Ma

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Efficient Circuit for Parallel Bit Reversal.

[BibT_eX]

[DOI]

Weijun Li

Feng Yu

Zhen-guo Ma

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Time Delay Estimation via Co-Prime Aliased Sparse FFT.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A novel nonlinear equalizer for extending the dynamic range of analog-to-digital converters.

[BibT_eX]

[DOI]

Xinfa Zhang

Feng Yu

IEICE Electron. Express, 2016

2015

A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm.

[BibT_eX]

[DOI]

Zhen-guo Ma

Xiaobo Yin

Feng Yu

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Pipelined Architecture for a Radix-2 Fast Walsh-Hadamard-Fourier Transform Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Block Region of Interest Method for Real-Time Implementation of Large and Scalable Image Reconstruction.

[BibT_eX]

[DOI]

Lin Li

Feng Yu

IEEE Signal Process. Lett., 2015

An Optimum Architecture for Continuous-Flow Parallel Bit Reversal.

[BibT_eX]

[DOI]

Chen Cheng

Feng Yu

IEEE Signal Process. Lett., 2015

A Cloud-Friendly Communication-Optimal Implementation for Strassen's Matrix Multiplication Algorithm.

[BibT_eX]

[DOI]

Jie Zhou

Feng Yu

IEICE Trans. Inf. Syst., 2015

A Combinatorial Aliasing-Based Sparse Fourier Transform.

[BibT_eX]

[DOI]

Pengcheng Qiu

Feng Yu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

2014

Radix-R WHT-FFT with Identical Stage-to-Stage Interconnection Pattern.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Efficient CORDIC-Based Processing Elements in Scalable Complex Matrix Inversion.

[BibT_eX]

[DOI]

Huan He

Feng Yu

Bei Zhao

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2013

Efficient Utilization of Vector Registers to Improve FFT Performance on SIMD Microprocessors.

[BibT_eX]

[DOI]

Feng Yu

Rui-feng Ge

Ze-ke Wang

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Block Processor: A resource-distributed architecture.

[BibT_eX]

[DOI]

Ze-ke Wang

Feng Yu

Xue Liu

Proceedings of the IEEE High Performance Extreme Computing Conference, 2013

2012

A Family of Fast Hadamard-Fourier Transform Algorithms.

[BibT_eX]

[DOI]

Teng Su

Feng Yu

IEEE Signal Process. Lett., 2012

2011

An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays.

[BibT_eX]

[DOI]

J. Zhejiang Univ. Sci. C, 2011

A pipelined architecture for normal I/O order FFT.

[BibT_eX]

[DOI]

Xue Liu

Feng Yu

Ze-ke Wang

J. Zhejiang Univ. Sci. C, 2011

Feng Yu

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