Rafael Serrano-Gotarredona

According to our database1, Rafael Serrano-Gotarredona authored at least 18 papers between 2003 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing- Learning-Actuating System for High-Speed Visual Object Recognition and Tracking.
IEEE Trans. Neural Networks, 2009

2008
On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing.
IEEE Trans. Neural Networks, 2008

LVDS interface for AER links with burst mode operation capability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
The Stochastic I-Pot: A Circuit Block for Programming Bias Currents.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

A Spatial Contrast Retina With On-Chip Calibration for Neuromorphic Spike-Based AER Vision Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Spike Events Processing for Vision Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

LVDS Serial AER Link performance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An AER Contrast Retina with On-Chip Calibration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

An arbitrary kernel convolution AER-transceiver chip for real-time image filtering.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-speed image processing with AER-based components.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A LVDS Serial AER Link.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

2004
Hardware implementation of complex reaction-diffusion neural networks using log-domain techniques.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

On mismatch properties of MOS and resistors calibrated ladder structures.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

On leakage current temperature characterization using sub-pico-ampere circuit techniques.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A new charge-packet driven mismatch-calibrated integrate-and-fire neuron for processing positive and negative signals in AER based systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Compact low-power calibration mini-DACs for neural arrays with programmable weights.
IEEE Trans. Neural Networks, 2003


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