Teresa Serrano-Gotarredona

According to our database1, Teresa Serrano-Gotarredona authored at least 93 papers between 1994 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
A Digital Neuromorphic Realization of the 2-D Wilson Neuron Model.
IEEE Trans. on Circuits and Systems, 2019

A Current Attenuator for Efficient Memristive Crossbars Read-Out.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Learning weights with STDP to build prototype images for classification.
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

Conversion of Synchronous Artificial Neural Network to Asynchronous Spiking Neural Network using sigma-delta quantization.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Event-Driven Stereo Visual Tracking Algorithm to Solve Object Occlusion.
IEEE Trans. Neural Netw. Learning Syst., 2018

Active Perception With Dynamic Vision Sensors. Minimum Saccades With Optimum Recognition.
IEEE Trans. Biomed. Circuits and Systems, 2018

Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Hybrid Neural Network, An Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Intrinsic Method for Fast Parameter Update on the SpiNNaker Platform.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Scene Context Classification with Event-Driven Spiking Deep Neural Networks.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.
IEEE Trans. Biomed. Circuits and Systems, 2017

Hardware implementation of convolutional STDP for on-line visual feature learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Live demonstration: Hardware implementation of convolutional STDP for on-line visual feature learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Spiking Hough for Shape Recognition.
Proceedings of the Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, 2017

2016
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links.
IEEE Trans. on Circuits and Systems, 2016

2015
ConvNets experiments on SpiNNaker.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Introduction to the IEEE-CASS workshop on micro/nanoelectronic circuits and systems.
Proceedings of the IEEE EUROCON 2015, 2015

2014
Neuromorphic Sensors, Vision.
Proceedings of the Encyclopedia of Computational Neuroscience, 2014

Retinomorphic Event-Based Vision Sensors: Bioinspired Cameras With Spiking Output.
Proceedings of the IEEE, 2014

Spike-based VITE control with dynamic vision sensor applied to an arm robot.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Event-driven stereo vision with orientation filters.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Event-driven sensing and processing for high-speed robotic vision.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Live demonstration: Event-driven sensing and processing for high-speed robotic vision.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
Multicasting Mesh AER: A Scalable Assembly Approach for Reconfigurable Neuromorphic Structured AER Systems. Application to ConvNets.
IEEE Trans. Biomed. Circuits and Systems, 2013

A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings.
IEEE Trans. Biomed. Circuits and Systems, 2013

Mapping from Frame-Driven to Frame-Free Event-Driven Vision Systems by Low-Rate Rate Coding and Coincidence Processing-Application to Feedforward ConvNets.
IEEE Trans. Pattern Anal. Mach. Intell., 2013

A 128×128 1.5% Contrast Sensitivity 0.9% FPN 3 µs Latency 4 mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Preamplifiers.
J. Solid-State Circuits, 2013

Improved contrast sensitivity DVS and its application to event-driven stereo vision.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A 0.35~µm Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links.
IEEE Trans. Biomed. Circuits and Systems, 2012

An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors.
J. Solid-State Circuits, 2012

A Real-Time, Event-Driven Neuromorphic System for Goal-Directed Attentional Selection.
Proceedings of the Neural Information Processing - 19th International Conference, 2012

Design of adaptive nano/CMOS neural architectures.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
An Instant-Startup Jitter-Tolerant Manchester-Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links.
IEEE Trans. on Circuits and Systems, 2011

A 32, times, 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput.
IEEE Trans. on Circuits and Systems, 2011

A 3.6 μ s Latency Asynchronous Frame-Free Event-Driven Dynamic-Vision-Sensor.
J. Solid-State Circuits, 2011

Voltage mode driver for low power transmission of high speed serial AER Links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Fast vision through frameless event-based sensing and convolutional processing: application to texture recognition.
IEEE Trans. Neural Networks, 2010

A Five-Decade Dynamic-Range Ambient-Light-Independent Calibrated Signed-Spatial-Contrast AER Retina With 0.1-ms Latency and Optional Time-to-First-Spike Mode.
IEEE Trans. on Circuits and Systems, 2010

On neuromorphic spiking architectures for asynchronous STDP memristive systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A signed spatial contrast event spike retina chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

On scalable spiking convnet hardware for cortex-like visual sensory processing systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Neocortical frame-free vision sensing and processing through scalable Spiking ConvNet hardware.
Proceedings of the International Joint Conference on Neural Networks, 2010

Spike-Based Convolutional Network for Real-Time Processing.
Proceedings of the 20th International Conference on Pattern Recognition, 2010

2009
CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing- Learning-Actuating System for High-Speed Visual Object Recognition and Tracking.
IEEE Trans. Neural Networks, 2009

OTA-C Oscillator with Low Frequency Variations for On-chip Clock Generation in Serial LVDS-AER Links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Mismatch Calibrated Bipolar Spatial Contrast AER Retina with Adjustable Contrast Threshold.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Advanced Vision Processing Systems: Spike-Based Simulation and Processing.
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2009

2008
On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing.
IEEE Trans. Neural Networks, 2008

A Calibration Technique for Very Low Current and Compact Tunable Neuromorphic Cells: Application to 5-bit 20-nA DACs.
IEEE Trans. on Circuits and Systems, 2008

LVDS interface for AER links with burst mode operation capability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

High-speed character recognition system based on a complex hierarchical AER architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Compact calibration circuit for large neuromorphic arrays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Fully digital AER convolution chip for vision processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Event based vision sensing and processing.
Proceedings of the International Conference on Image Processing, 2008

2007
The Stochastic I-Pot: A Circuit Block for Programming Bias Currents.
IEEE Trans. on Circuits and Systems, 2007

A Spatial Contrast Retina With On-Chip Calibration for Neuromorphic Spike-Based AER Vision Systems.
IEEE Trans. on Circuits and Systems, 2007

An Accurate Automatic Quality-Factor Tuning Scheme for Second-Order LC Filters.
IEEE Trans. on Circuits and Systems, 2007

On an Efficient CAD Implementation of the Distance Term in Pelgrom's Mismatch Model.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Spike Events Processing for Vision Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Physical Interpretation of the Distance Term in Pelgrom's Mismatch Model results in very Efficient CAD.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An AER Contrast Retina with On-Chip Calibration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A Low-Power Current Mode Fuzzy-ART Cell.
IEEE Trans. Neural Networks, 2006

A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems.
IEEE Trans. on Circuits and Systems, 2006

An arbitrary kernel convolution AER-transceiver chip for real-time image filtering.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-speed image processing with AER-based components.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

2004
A precise 90° quadrature OTA-C oscillator tunable in the 50-130-MHz range.
IEEE Trans. on Circuits and Systems, 2004

Hardware implementation of complex reaction-diffusion neural networks using log-domain techniques.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A precise CMOS mismatch model for analog design from weak to strong inversion.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

On mismatch properties of MOS and resistors calibrated ladder structures.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

On leakage current temperature characterization using sub-pico-ampere circuit techniques.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A new charge-packet driven mismatch-calibrated integrate-and-fire neuron for processing positive and negative signals in AER based systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A precise 90/spl deg/ quadrature OTA-C VCO between 50-130 MHz.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Log-domain implementation of complex dynamics reaction-diffusion neural networks.
IEEE Trans. Neural Networks, 2003

Compact low-power calibration mini-DACs for neural arrays with programmable weights.
IEEE Trans. Neural Networks, 2003

2000
A Programmable VLSI Filter Architecture for Application in Real-Time Vision Processing Systems.
Int. J. Neural Syst., 2000

A new strong inversion 5-parameter transistor mismatch model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A methodology for MOS transistor mismatch parameter extraction and mismatch simulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Programmable Kernel Analog VLSI Convolution Chip for Real Time Vision Processing.
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

1999
On the Design of Second Order Dynamics Reaction-Diffusion CNNs.
VLSI Signal Processing, 1999

Adaptive Resonance Theory Microchips.
Proceedings of the Foundations and Tools for Neural Modeling, 1999

A general subthreshold MOS translinear theorem.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Programmable 2D image filter for AER vision processing.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997
An ART1 microchip and its use in multi-ART1 systems.
IEEE Trans. Neural Networks, 1997

1996
A real-time clustering microchip neural engine.
IEEE Trans. VLSI Syst., 1996

A Modified ART 1 Algorithm more Suitable for VLSI Implementations.
Neural Networks, 1996

1995
Experimental Results of an Analog Current-Mode ART1 Chip.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
A Real Time Clustering CMOS Neural Engine.
Proceedings of the Advances in Neural Information Processing Systems 7, 1994

A Modular Current-Mode High-Precision Winner-Take-All Circuit.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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