Luis A. Camuñas-Mesa

Orcid: 0000-0002-3425-854X

According to our database1, Luis A. Camuñas-Mesa authored at least 36 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2023
Using ANNs to predict the evolution of spectrum occupancy in cognitive-radio systems.
Integr., November, 2023

Compact Functional Testing for Neuromorphic Computing Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Combining Software-Defined Radio Learning Modules and Neural Networks for Teaching Communication Systems Courses.
Inf., 2023

A Fully Digital Relaxation-Aware Analog Programming Technique for HfOx RRAM Arrays.
CoRR, 2023

A multi-core memristor chip for Stochastic Binary STDP.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Study of foveation mechanisms in Dynamic Vision Sensors.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022
A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Using ANNs to Predict Frequency Spectrum Occupancy in Cognitive-Radio Receivers.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

Reliability Analysis of a Spiking Neural Network Hardware Accelerator.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration.
IEEE Access, 2021

Implementation of Binary Stochastic STDP Learning Using Chalcogenide-Based Memristive Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Cognitive Radio Circuits and Systems - Application to Digitizers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Neuron Fault Tolerance in Spiking Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Low Order Wideband Multiplierless Comb Compensator.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020


Spiking Neuron Hardware-Level Fault Modeling.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Using Neural Networks for Optimum band selection in Cognitive-Radio Systems.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Implementation of a tunable spiking neuron for STDP with memristors in FDSOI 28nm.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
Self-Testing Analog Spiking Neuron Circuit.
Proceedings of the 16th International Conference on Synthesis, 2019

Low-power hardware implementation of SNN with decision block for recognition tasks.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
Event-Driven Stereo Visual Tracking Algorithm to Solve Object Occlusion.
IEEE Trans. Neural Networks Learn. Syst., 2018

Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2014
Event-driven stereo vision with orientation filters.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Event-driven sensing and processing for high-speed robotic vision.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Live demonstration: Event-driven sensing and processing for high-speed robotic vision.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
A Detailed and Fast Model of Extracellular Recordings.
Neural Comput., 2013

2012
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors.
IEEE J. Solid State Circuits, 2012

2011
A 32, times, 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010
Fast vision through frameless event-based sensing and convolutional processing: application to texture recognition.
IEEE Trans. Neural Networks, 2010

On scalable spiking convnet hardware for cortex-like visual sensory processing systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Neocortical frame-free vision sensing and processing through scalable Spiking ConvNet hardware.
Proceedings of the International Joint Conference on Neural Networks, 2010

2009
CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing- Learning-Actuating System for High-Speed Visual Object Recognition and Tracking.
IEEE Trans. Neural Networks, 2009

2008
Fully digital AER convolution chip for vision processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
The Stochastic I-Pot: A Circuit Block for Programming Bias Currents.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

2004
On leakage current temperature characterization using sub-pico-ampere circuit techniques.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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