Bernabé Linares-Barranco
Orcid: 0000-0002-1813-4889
According to our database1,
Bernabé Linares-Barranco
authored at least 173 papers
between 1991 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2010, "For contributions to the design and application of linear and nonlinear circuits in neuromorphic systems".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
IEEE Trans. Biomed. Circuits Syst., February, 2024
Integrating Visual Perception With Decision Making in Neuromorphic Fault-Tolerant Quadruplet-Spike Learning Framework.
IEEE Trans. Syst. Man Cybern. Syst., 2024
2023
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
Smart Traffic Navigation System for Fault-Tolerant Edge Computing of Internet of Vehicle in Intelligent Transportation Gateway.
IEEE Trans. Intell. Transp. Syst., November, 2023
Biol. Cybern., October, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
CoRR, 2023
Hardware-Efficient Design and Implementation of a Spiking Neural Model With Noisy Astrocyte.
IEEE Access, 2023
Performance comparison of DVS data spatial downscaling methods using Spiking Neural Networks.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023
Empirical study on the efficiency of Spiking Neural Networks with axonal delays, and algorithm-hardware benchmarking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
An Event-Based Tracking Control Framework for Multirotor Aerial Vehicles Using a Dynamic Vision Sensor and Neuromorphic Hardware.
IROS, 2023
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Trans. Neural Networks Learn. Syst., 2022
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase.
IEEE Trans. Neural Networks Learn. Syst., 2022
IEEE Trans. Neural Networks Learn. Syst., 2022
Pattern Anal. Appl., 2022
Neuromorph. Comput. Eng., 2022
Neurocomputing, 2022
A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Proceedings of the 17th International Joint Conference on Computer Vision, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Neutron-Induced, Single-Event Effects on Neuromorphic Event-Based Vision Sensor: A First Step and Tools to Space Applications.
IEEE Access, 2021
Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration.
IEEE Access, 2021
Proceedings of the IEEE International Symposium on Medical Measurements and Applications, 2021
Implementation of Binary Stochastic STDP Learning Using Chalcogenide-Based Memristive Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Baseline Features Extraction from Microelectrode Array Recordings in an in vitro model of Acute Seizures using Digital Signal Processing for Electronic Implementation.
Proceedings of the 2021 IEEE International Conference on Omni-Layer Intelligent Systems, 2021
Novel programmable single pulse generator for producing pulse widths in different time scales.
Proceedings of the 18th International Conference on Content-Based Multimedia Indexing, 2021
2020
Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits - Application to Voltage-Controlled Ring Oscillators and Frequency-Based ΣΔ ADCs.
IEEE Trans. Circuits Syst., 2020
Hardware Implementation of Deep Network Accelerators Towards Healthcare and Biomedical Applications.
IEEE Trans. Biomed. Circuits Syst., 2020
Event-driven implementation of deep spiking convolutional neural networks for supervised classification using the SpiNNaker neuromorphic platform.
Neural Networks, 2020
Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Auxiliary Pulse-Extender and Current-Attenuator Circuits for Flexible Interaction with Memristive Crossbars in SNNs.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the 15th IEEE International Conference on Automatic Face and Gesture Recognition, 2020
Oscillatory Hebbian Rule (OHR): An adaption of the Hebbian rule to Oscillatory Neural Networks.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
A Current-Attenuator for Performing Read Operation in Memristor-Based Spiking Neural Networks.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Digital hardware realization of a novel adaptive ink drop spread operator and its application in modeling and classification and on-chip training.
Int. J. Mach. Learn. Cybern., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Digital-Signal-Processor Realization of Izhikevich Neural Network for Real-Time Interaction with Electrophysiology Experiments.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019
Conversion of Synchronous Artificial Neural Network to Asynchronous Spiking Neural Network using sigma-delta quantization.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
Proceedings of the Handbook of Memristor Networks., 2019
2018
IEEE Trans. Neural Networks Learn. Syst., 2018
Active Perception With Dynamic Vision Sensors. Minimum Saccades With Optimum Recognition.
IEEE Trans. Biomed. Circuits Syst., 2018
Digital Implementation of the Two-Compartmental Pinsky-Rinzel Pyramidal Neuron Model.
IEEE Trans. Biomed. Circuits Syst., 2018
Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Hybrid Neural Network, An Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 14th IEEE International Conference on Intelligent Computer Communication and Processing, 2018
2017
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.
IEEE Trans. Biomed. Circuits Syst., 2017
IEEE Trans. Biomed. Circuits Syst., 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Live demonstration: Hardware implementation of convolutional STDP for on-line visual feature learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, 2017
2016
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
2015
Feedforward Categorization on AER Motion Events Using Cortex-Like Features in a Spiking Neural Network.
IEEE Trans. Neural Networks Learn. Syst., 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Fast Pipeline 128×128 pixel spiking convolution core for event-driven vision processing in FPGAs.
Proceedings of the International Conference on Event-based Control, 2015
Proceedings of the International Conference on Event-based Control, 2015
2014
Proceedings of the Encyclopedia of Computational Neuroscience, 2014
Proc. IEEE, 2014
Spiking neuro-fuzzy clustering system and its memristor crossbar based implementation.
Microelectron. J., 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
Live demonstration: Event-driven sensing and processing for high-speed robotic vision.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
2013
Multicasting Mesh AER: A Scalable Assembly Approach for Reconfigurable Neuromorphic Structured AER Systems. Application to ConvNets.
IEEE Trans. Biomed. Circuits Syst., 2013
A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings.
IEEE Trans. Biomed. Circuits Syst., 2013
Mapping from Frame-Driven to Frame-Free Event-Driven Vision Systems by Low-Rate Rate Coding and Coincidence Processing-Application to Feedforward ConvNets.
IEEE Trans. Pattern Anal. Mach. Intell., 2013
A 128×128 1.5% Contrast Sensitivity 0.9% FPN 3 µs Latency 4 mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Preamplifiers.
IEEE J. Solid State Circuits, 2013
CoRR, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
A 0.35~µm Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links.
IEEE Trans. Biomed. Circuits Syst., 2012
Efficient Feedforward Categorization of Objects and Human Postures with Address-Event Image Sensors.
IEEE Trans. Pattern Anal. Mach. Intell., 2012
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors.
IEEE J. Solid State Circuits, 2012
A Real-Time, Event-Driven Neuromorphic System for Goal-Directed Attentional Selection.
Proceedings of the Neural Information Processing - 19th International Conference, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
An Instant-Startup Jitter-Tolerant Manchester-Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
A 32, times, 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE J. Solid State Circuits, 2011
CoRR, 2011
Visual AER-based Processing with Convolutions for a Parallel Supercomputer.
Proceedings of the SIGMAP 2011, 2011
Proceedings of the Advances in Computational Intelligence, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Fast vision through frameless event-based sensing and convolutional processing: application to texture recognition.
IEEE Trans. Neural Networks, 2010
A Five-Decade Dynamic-Range Ambient-Light-Independent Calibrated Signed-Spatial-Contrast AER Retina With 0.1-ms Latency and Optional Time-to-First-Spike Mode.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
On scalable spiking convnet hardware for cortex-like visual sensory processing systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Neocortical frame-free vision sensing and processing through scalable Spiking ConvNet hardware.
Proceedings of the International Joint Conference on Neural Networks, 2010
Proceedings of the 20th International Conference on Pattern Recognition, 2010
A 100dB dynamic range event-driven spatial contrast sensor with 100μs response time and Time-to-First-Spike mode.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing- Learning-Actuating System for High-Speed Visual Object Recognition and Tracking.
IEEE Trans. Neural Networks, 2009
OTA-C Oscillator with Low Frequency Variations for On-chip Clock Generation in Serial LVDS-AER Links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
A Mismatch Calibrated Bipolar Spatial Contrast AER Retina with Adjustable Contrast Threshold.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2009
2008
On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing.
IEEE Trans. Neural Networks, 2008
A Calibration Technique for Very Low Current and Compact Tunable Neuromorphic Cells: Application to 5-bit 20-nA DACs.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
High-speed character recognition system based on a complex hierarchical AER architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Conference on Image Processing, 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
A Spatial Contrast Retina With On-Chip Calibration for Neuromorphic Spike-Based AER Vision Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Neurocomputing, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A Physical Interpretation of the Distance Term in Pelgrom's Mismatch Model results in very Efficient CAD.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Proceedings of the Advances in Neural Information Processing Systems 18 [Neural Information Processing Systems, 2005
Proceedings of the Computational Intelligence and Bioinspired Systems, 2005
2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Hardware implementation of complex reaction-diffusion neural networks using log-domain techniques.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
On mismatch properties of MOS and resistors calibrated ladder structures.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
On leakage current temperature characterization using sub-pico-ampere circuit techniques.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A new charge-packet driven mismatch-calibrated integrate-and-fire neuron for processing positive and negative signals in AER based systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A precise 90° quadrature OTA-C VCO between 50-130 MHz.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
On synthetic AER generation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
IEEE Trans. Neural Networks, 2003
IEEE Trans. Neural Networks, 2003
IEEE Trans. Neural Networks, 2003
IEEE J. Solid State Circuits, 2003
MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design.
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the ESSCIRC 2003, 2003
2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
2000
A Programmable VLSI Filter Architecture for Application in Real-Time Vision Processing Systems.
Int. J. Neural Syst., 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
A methodology for MOS transistor mismatch parameter extraction and mismatch simulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000
1999
Proceedings of the Foundations and Tools for Neural Modeling, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
1998
IEEE J. Solid State Circuits, 1998
1997
IEEE Trans. Neural Networks, 1997
1996
IEEE Trans. Very Large Scale Integr. Syst., 1996
Neural Networks, 1996
1995
Experimental Results of an Analog Current-Mode ART1 Chip.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
Proceedings of the Advances in Neural Information Processing Systems 7, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
IEEE Trans. Neural Networks, 1993
A Model for VLSI Implementation of CNN Image Processing Chips Using Current-mode Techniques.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
1991
Proceedings of the Artificial Neural Networks, 1991