Rafic Ayoubi

According to our database1, Rafic Ayoubi authored at least 29 papers between 1994 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
A Self Referencing Technique for the RC-pLMS Adaptive Beamformer and Its Hardware Implementation.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2021

2020
A Pipelined Reduced Complexity Two-Stages Parallel LMS Structure for Adaptive Beamforming.
IEEE Trans. Circuits Syst., 2020

Two Stages Parallel LMS Structure: A Pipelined Hardware Architecture.
Proceedings of the 28th European Signal Processing Conference, 2020

2019
FPGA Realization of MRC with Optimized Exponent for Adaptive Array Antennas.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

Hardware Architecture for a Bit-Serial Odd-Even Transposition Sort Network with On-The-Fly Compare and Swap.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

Hardware Architecture For A Shift-Based Parallel Odd-Even Transposition Sorting Network.
Proceedings of the Fourth International Conference on Advances in Computational Tools for Engineering Applications, 2019

2018
Constant Time Hardware Architecture for a Gaussian Smoothing Filter.
Proceedings of the International Conference on Signal Processing and Information Security, 2018

2017
Hardware and software implementation of a stereoscopic image compression technique for internet connected devices.
Proceedings of the 2017 International Symposium on Networks, Computers and Communications, 2017

2016
Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs.
Neurocomputing, 2016

FPGA hardware architecture for stereoscopic image compression based on block matching, watermarking and hamming code.
Proceedings of the International Image Processing, Applications and Systems, 2016

2014
SEU fault-injection at system level: Method, tools and preliminary results.
Proceedings of the 15th Latin American Test Workshop, 2014

Real-time Parallelized Hybrid Median Filter for speckle removal in ultrasound images.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

2013
Fault-tolerance capabilities of a software-implemented Hopfield Neural Network.
Proceedings of the Third International Conference on Communications and Information Technology, 2013

2011
A new fault injection approach to study the impact of bitflips in the configuration of SRAM-based FPGAs.
Int. Arab J. Inf. Technol., 2011

An Optimal Implementation on FPGA of a Hopfield Neural Network.
Adv. Artif. Neural Syst., 2011

TALS: Trigonometry-based Ad-hoc Localization System for wireless sensor networks.
Proceedings of the 7th International Wireless Communications and Mobile Computing Conference, 2011

2009
Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
OV-CDMA System: Concept and Implementation.
EURASIP J. Wirel. Commun. Netw., 2008

2007
Design and Realization of Analog Phi-Function for LDPC Decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
FPGA-based transmitter-receiver architecture of an overlapped FFH-CDMA system: design and simulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
A Survey on Fault Injection Techniques.
Int. Arab J. Inf. Technol., 2004

Hopfield associative memory on mesh.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Efficient Mapping Algorithm of Multilayer Neural Network on Torus Architecture.
IEEE Trans. Parallel Distributed Syst., 2003

Fault Tolerant Hopfield Associative Memory on Torus.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

1998
Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997
An Efficient Mapping Algorithm of Multilayer Perceptron on Mesh-connected Architectures.
Parallel Algorithms Appl., 1997

1996
The Extended Cube Connected Cycles: An Efficient Interconnection for Massively Parallel Systems.
IEEE Trans. Computers, 1996

1994
Bitonic Sort on the Connection Machine.
Parallel Algorithms Appl., 1994


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