Magdy A. Bayoumi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Reduced-Gate Convolutional LSTM Architecture for Next-Frame Video Prediction Using Predictive Coding.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2019

An Analysis of Univariate and Multivariate Electrocardiography Signal Classification.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference On Machine Learning And Applications, 2019

Unsupervised Ranking of Numerical Observations based on Magnetic Properties and Correlation Coefficient.

[BibT_eX]

[DOI]

Proceedings of the 52nd Hawaii International Conference on System Sciences, 2019

Lightweight Cryptography for Internet of Insecure Things: A Survey.

[BibT_eX]

[DOI]

Indira Kalyan Dutta

Bhaskar Ghosh

Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

Semi-supervised Learning for Epileptic Focus Localization Using Deep Convolutional Autoencoder.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018

Cost-Efficient and Robust On-Demand Video Transcoding Using Heterogeneous Cloud Services.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2018

Emerging Technologies: IoT, Big Data, and CPS with Sensory Systems.

[BibT_eX]

[DOI]

J. Sensors, 2018

Deep Gated Recurrent and Convolutional Network Hybrid Model for Univariate Time Series Classification.

[BibT_eX]

[DOI]

CoRR, 2018

Reduced-Gate Convolutional LSTM Using Predictive Coding for Spatiotemporal Prediction.

[BibT_eX]

[DOI]

CoRR, 2018

Hotspot-aware task-resource co-allocation for heterogeneous many-core networks-on-chip.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2018

Power- Thermal Aware Balanced Task-Resource Co-Allocation in Heterogeneous Many CPU-GPU Cores NoC in Dark Silicon Era.

[BibT_eX]

[DOI]

Md Farhadur Reza

Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Flexible Self-Healing Router for Reliable and High-Performance Network-an-Chips Architecture.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Epileptic Seizure Detection using Deep Convolutional Autoencoder.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Modeling and performance simulation of PULSE and MCMAC protocols in RFID-based IoT network using OMNeT++.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Conference on RFID, 2018

Deep Convolutional Bidirectional LSTM Recurrent Neural Network for Epileptic Seizure Detection.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

A hardware obfuscation technique for manufacturing a secure 3D IC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

FPGA Implementation of High Accuracy Automatic Epileptic Seizure Detection System.

[BibT_eX]

[DOI]

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A Perceptron-Inspired Technique for Hardware Obfuscation.

[BibT_eX]

[DOI]

Siroos Madani

Mohammad R. Madani

Proceedings of the 19th International Workshop on Microprocessor and SOC Test and Verification, 2018

Neuro-NoC: Energy Optimization in Heterogeneous Many-Core NoC using Neural Networks in Dark Silicon Era.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Cost-Effective Self-Healing Approach for Reliable Hardware Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Empirical Activation Function Effects on Unsupervised Convolutional LSTM Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE 30th International Conference on Tools with Artificial Intelligence, 2018

Semi-Supervised Deep Learning System for Epileptic Seizures Onset Prediction.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Machine Learning and Applications, 2018

An Efficient Approach for Neural Network Architecture.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Spectrum-Awareness-Based Performance and Scalability of Cognitive Radio Networks.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Conference on Communications Workshops, 2018

A Low Power Hardware Implementation of Multi-Object DPM Detector for Autonomous Driving.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

A Comparative Analysis on Resource Discovery Protocols for The Internet of Things.

[BibT_eX]

[DOI]

Khalid Elgazzar

Proceedings of the IEEE Global Communications Conference, 2018

Deep Learning based Reliable Early Epileptic Seizure Predictor.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017

It was Really Lagniappe!: Highlights from ICASSP 2017 in New Orleans [Conference Highlights].

[BibT_eX]

[DOI]

IEEE Signal Process. Mag., 2017

Redundant Bit Security in RFIDs: Architecture Design and Security Performance Evaluation.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2017

Framework for generating and designing spectrum awareness modules for opportunistic networking.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017

Optimizing the heterogeneous network on-chip design in manycore architectures.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Router-level performance driven dynamic management in hierarchical networks-on-chip.

[BibT_eX]

[DOI]

Mingmin Bai

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A highly reliable dual-arbiter PUF for lightweight authentication protocols.

[BibT_eX]

[DOI]

Haytham Idriss

Proceedings of the IEEE International Conference on RFID Technology & Application, 2017

Lightweight highly secure PUF protocol for mutual authentication and secret message exchange.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on RFID Technology & Application, 2017

BCI/AIS low power adaptive architecture for early prediction of epilepsy seizures.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A novel approach towards less area overhead self-healing hardware systems.

[BibT_eX]

[DOI]

Omar K. Eldash

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A Security-Aware Pre-partitioning Technique for 3D Integrated Circuits.

[BibT_eX]

[DOI]

Siroos Madani

Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

Cost Efficient Repository Management for Cloud-Based On-demand Video Streaming.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Mobile Cloud Computing, 2017

Efficient Reconfigurable Global Network-on-Chip Designs towards Heterogeneous CPU-GPU Systems: An Application-Aware Approach.

[BibT_eX]

[DOI]

Tung Thanh Le

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Fast deep pyramid DPM object detection with region proposal networks.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Signal Processing and Information Technology, 2017

Real-time streaming challenges in Internet of Video Things (IoVT).

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Dark silicon-power-thermal aware runtime mapping and configuration in heterogeneous many-core NoC.

[BibT_eX]

[DOI]

Md Farhadur Reza

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Fault tolerant techniques for TSV-based interconnects in 3-D ICs.

[BibT_eX]

[DOI]

Siroos Madani

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Self-healing router architecture for reliable network-on-chips.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

On reconfigurable fabrics for intelligent hardware systems.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Correlation-based detection of TCM signals for cognitive radios.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

Repair techniques for aged TSVs in 3D integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

On on-chip intelligence paradigms.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016

A PUF-based paradigm for IoT security.

[BibT_eX]

[DOI]

Haytham Idriss

Proceedings of the 3rd IEEE World Forum on Internet of Things, 2016

Introducing a Novel Smart Design Framework for a Reconfigurable Multi-Processor Systems-on-Chip (MPSoC) Architecture.

[BibT_eX]

[DOI]

Anandi Dutta

Proceedings of the 2016 IEEE International Conference on Smart Computing, 2016

A Survey on the power and robustness of FinFET SRAM.

[BibT_eX]

[DOI]

Mahmoud Darwich

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Fast region-based DPM object detection for autonomous vehicles.

[BibT_eX]

[DOI]

Alaa Ali

Oladiran G. Olaleye

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

An Energy-Detection-Based Cooperative Spectrum Sensing Scheme for Minimizing the Effects of NPEE and RSPF.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM International Conference on Modeling, 2016

Secure End-to-End key establishment protocol for resource-constrained healthcare sensors in the context of IoT.

[BibT_eX]

[DOI]

Muhammad A. Iqbal

Proceedings of the International Conference on High Performance Computing & Simulation, 2016

On sub-Nyquist spectrum sensing for wideband cognitve radios.

[BibT_eX]

[DOI]

Mohamed Shaban

Proceedings of the Eighth International Conference on Ubiquitous and Future Networks, 2016

Keynotes and plenary: Keynote #1: "Be Careful: I can read your mind".

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Microelectronics, 2016

Towards real-time DPM object detector for driver assistance.

[BibT_eX]

[DOI]

Alaa Ali

Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

A Novel Authentication and Key Agreement Protocol for Internet of Things Based Resource-Constrained Body Area Sensors.

[BibT_eX]

[DOI]

Muhammad A. Iqbal

Proceedings of the 4th IEEE International Conference on Future Internet of Things and Cloud Workshops, 2016

CVSS: A Cost-Efficient and QoS-Aware Video Streaming Using Cloud Services.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016

High Performance On-demand Video Transcoding Using Cloud Services.

[BibT_eX]

[DOI]

Xiangbo Li

Mohsen Amini Salehi

Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016

VLSC: Video Live Streaming Using Cloud Services.

[BibT_eX]

[DOI]

Xiangbo Li

Mohsen Amini Salehi

Proceedings of the 2016 IEEE International Conferences on Big Data and Cloud Computing (BDCloud), 2016

2015

Performance Evaluation and Design Optimization for Flexible Multiple Instruction Multiple Data Elliptic Curve Cryptography Crypto Architecture.

[BibT_eX]

[DOI]

J. Low Power Electron., 2015

Standardization of cognitive radio networking: a comprehensive survey.

[BibT_eX]

[DOI]

Ann. des Télécommunications, 2015

Low-latency power-efficient adaptive router design for network-on-chip.

[BibT_eX]

[DOI]

Nasim Nasirian

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Toward fast low power adaptive spike sorting VLSI chip design for wireless BCI implants.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

An overview of IEEE standardization efforts for cognitive radio networks.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Decentralized clustering in VANET using adaptive resonance theory.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Implementable Spike Sorting techniques for VLSI wireless BCI/BMI implants: A survey.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

Green energy solution for femtocell power control in massive deployments.

[BibT_eX]

[DOI]

Mazen Al Haddad

Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

Building and Evaluating COTS Based Optical Interlinks for Nanosatellites.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Communication and Networks, 2015

Adaptive neural matching online spike sorting VLSI chip design for wireless BCI implants.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

ASIC implementation of a computationally efficient compressive sensing detection method using least squares optimization in 45 nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

2014

Video Surveillance for Sensor Platforms - Algorithms and Architectures

[BibT_eX]

[DOI]

Lecture Notes in Electrical Engineering 114, Springer, ISBN: 978-1-4614-1856-6, 2014

Optimal Probabilistic Encryption for Secure Detection in Wireless Sensor Networks.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2014

A Clock gated Successive Approximation Register for a/d Conversions.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2014

Evaluation of Femtocell Technology Challenges and Its Power Control Methodologies for Green Heterogeneous Networks.

[BibT_eX]

[DOI]

Mazen Al Haddad

Proceedings of the SMARTGREENS 2014, 2014

The challenges towards energy-efficient cognitive radio networking.

[BibT_eX]

[DOI]

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

A cluster-based key management framework for resource constraint networks.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Information Reuse and Integration, 2014

Investigating the feasibility of LEAP+ in ZigBee specification.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Information Reuse and Integration, 2014

Energy scavenging and storage using through silicon vias to reduce power consumption in 3D ICs.

[BibT_eX]

[DOI]

Robert Minvielle

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

OAPM: Fine-grained operand-aware power management with fast reaction time.

[BibT_eX]

[DOI]

Salirti N. Farah

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

FinFET based SRAM design: A survey on device, circuit, and technology issues.

[BibT_eX]

[DOI]

Anandi Dutta

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Real-time Parallelized Hybrid Median Filter for speckle removal in ultrasound images.

[BibT_eX]

[DOI]

Randa Ayoubi

Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

Hybrid wavelet - DCT intra prediction for H.264/AVC interactive encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE China Summit & International Conference on Signal and Information Processing, 2014

2013

Editorial.

[BibT_eX]

[DOI]

Mohammad M. Mansour

Brian L. Evans

J. Signal Process. Syst., 2013

MIRF: A Multimodal Image Registration and Fusion Module Based on DT-CWT.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2013

Efficient 45nm ASIC Architecture for Full-Search Free Intra Prediction in Real-Time H.264/AVC Decoder.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2013

Design, Implementation and Characterization of Practical Distributed Cognitive Radio Networks.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2013

A 3.1 GB/s, 8 Kb, ZERO PRECHARGE, PIPELINED, HIGHLY STABLE 2-PORT 8T SRAM DESIGN IN 65 nm.

[BibT_eX]

[DOI]

Krishna Prasad Balusu

Chandra Sekhar Gurram

J. Circuits Syst. Comput., 2013

Editorial: Low-Power, Intelligent, and Secure Solutions for Realization of Internet of Things.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

Hardware Acceleration of the Gipps Model for Real-Time Traffic Simulation

[BibT_eX]

[DOI]

Salim Farah

CoRR, 2013

A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic.

[BibT_eX]

[DOI]

Salim Farah

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

An efficient compressive wideband spectrum sensing architecture for cognitive radios.

[BibT_eX]

[DOI]

Mohamed Shaban

Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Novel clock gating techniques for low power flip-flops and its applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

On Through Silicon Vias as used in three dimensional integrated circuits.

[BibT_eX]

[DOI]

Robert Minvielle

Proceedings of the 4th Annual International Conference on Energy Aware Computing Systems and Applications, 2013

A Novel Authenticated Encryption Algorithm for RFID Systems.

[BibT_eX]

[DOI]

Zahra Jeddi

Esmaeil Amini

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A novel clustering paradigm for key pre-distribution: Toward a better security in homogenous WSNs.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Consumer Communications and Networking Conference, 2013

2012

Resource-Aware Data Fusion Algorithms for Wireless Sensor Networks

[BibT_eX]

[DOI]

Lecture Notes in Electrical Engineering 118, Springer, ISBN: 978-1-4614-1349-3, 2012

Opportunistic Spectrum Access: From Theory to Practice.

[BibT_eX]

[DOI]

IEEE Veh. Technol. Mag., 2012

Fast Motion Estimation System Using Dynamic Models for H.264/AVC Video Coding.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2012

A Low-Power Parallel Architecture for Finite Galois Field GF(2m) Arithmetic Operations for Elliptic Curve Cryptography.

[BibT_eX]

[DOI]

J. Low Power Electron., 2012

High-speed Motion Estimation Architecture for Real-time Video Transmission.

[BibT_eX]

[DOI]

Comput. J., 2012

Hardware architecture for fast Intra mode and direction prediction in real-time MPEG-2 to H.264/AVC transcoder.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on a World of Wireless, 2012

Highly stable, dual-port, sub-threshold 7T SRAM cell for ultra-low power application.

[BibT_eX]

[DOI]

Srikanth Bakkamanthala

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Secure localization for wireless sensor networks using decentralized dynamic key generation.

[BibT_eX]

[DOI]

Proceedings of the 8th International Wireless Communications and Mobile Computing Conference, 2012

Experimental evaluation of Opportunistic Spectrum Access in distributed cognitive radio networks.

[BibT_eX]

[DOI]

Proceedings of the 8th International Wireless Communications and Mobile Computing Conference, 2012

Structure generation and design of tracking ADCs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An ultra-low power current reused CMOS low noise amplifier for x-band space application.

[BibT_eX]

[DOI]

Saeid Yasami

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

CEMS-PG: A parametrized algorithm for balanced partitioning and wakeup of power gated circuits.

[BibT_eX]

[DOI]

Salim Farah

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A high-throughput ECC architecture.

[BibT_eX]

[DOI]

Esmaeil Amini

Zahra Jeddi

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

An energy-efficient 32-bit RISC processor for sensor platform in 90nm technology.

[BibT_eX]

[DOI]

Krishna Prasad Balusu

Proceedings of the International Conference on Energy Aware Computing, 2012

Green arithmetic logic unit.

[BibT_eX]

[DOI]

Mazen Al Haddad

Zaghloul ElSayed

Proceedings of the International Conference on Energy Aware Computing, 2012

Comparing performance metrics of a parallel ECC architecture vs. input data patterns and granularity.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Energy Aware Computing, 2012

RBS: Redundant Bit Security Algorithm for RFID Systems.

[BibT_eX]

[DOI]

Zahra Jeddi

Esmaeil Amini

Proceedings of the 21st International Conference on Computer Communications and Networks, 2012

Testbed implementation for Autonomic Network Performance Management of wireless mesh networks.

[BibT_eX]

[DOI]

Proceedings of the Workshops Proceedings of the Global Communications Conference, 2012

2011

An Efficient Adaptive High Speed Manipulation Architecture for Fast Variable Padding Frequency Domain Motion Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Memory-Efficient Architecture for Hysteresis Thresholding and Object Feature Extraction.

[BibT_eX]

[DOI]

IEEE Trans. Image Process., 2011

Remote Measuring for Sand in Pipelines Using Wireless Sensor Network.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2011

A Bit-Interleaved 2-Port Subthreshold 6T SRAM Array with High Write-Ability and SNM-Free Read in 90 nm.

[BibT_eX]

[DOI]

J. Low Power Electron., 2011

A Flexible Architecture for Finite Field Galois Fields(2m) Arithmetic Processor.

[BibT_eX]

[DOI]

J. Low Power Electron., 2011

Probabilistic framework for opportunistic spectrum management in cognitive ad hoc networks.

[BibT_eX]

[DOI]

EURASIP J. Wirel. Commun. Netw., 2011

Low-Power Distributed Kalman Filter for Wireless Sensor Networks.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2011

Energy-Aware Distributed QR Decomposition on Wireless Sensor Nodes.

[BibT_eX]

[DOI]

Sherine Abdelhak

Rabi S. Chaudhuri

Chandra Sekhar Gurram

Comput. J., 2011

Rate-adaptive probabilistic spectrum management for cognitive radio networks.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Symposium on a World of Wireless, 2011

De-Cache: A novel caching scheme for large-scale NoC based multiprocessor systems-on-chips.

[BibT_eX]

[DOI]

Azeez Sanusi

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Energy-efficient XOR gate with embedded level conversion for serial-link encoding.

[BibT_eX]

[DOI]

Jared Tessier

Randa Ayoubi

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

EVA-MAC: An event-based adaptive medium access control for wireless sensor networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Frequency domain: Efficient and high speed technology for video transmission.

[BibT_eX]

[DOI]

Sherif El-Etriby

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

High speed intra mode and direction prediction for MPEG-2 to H.264/AVC realtime transcoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

TALS: Trigonometry-based Ad-hoc Localization System for wireless sensor networks.

[BibT_eX]

[DOI]

Proceedings of the 7th International Wireless Communications and Mobile Computing Conference, 2011

A 90 nm low-power successive approximation register for A/D conversions.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A clock gated flip-flop for low power applications in 90 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

P2E-DWT: A parallel and pipelined efficient VLSI architecture of 2-D Discrete Wavelet Transform.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

ETSSI: Energy-based Task Scheduling Simulator for wireless sensor networks.

[BibT_eX]

[DOI]

Sherine Abdelhak

Chandra Sekhar Gurram

Jared Tessier

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Distributed Kalman Filter using fast polynomial filter.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

High-performance asic architecture for hysteresis thresholding and component feature extraction in limited-resource applications.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Image Processing, 2011

2010

PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2010

Gaussian pulse approximation using standard CMOS and its application for sub-GHz UWB impulse radio.

[BibT_eX]

[DOI]

Xiaodong Zhang

Int. J. Circuit Theory Appl., 2010

An efficient area manipulation architecture for frequency domain encoding process.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A compact single-pass architecture for hysteresis thresholding and component labeling.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2010

A fast discrete transform architecture for Frequency Domain Motion Estimation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2010

ASPEN: An Asynchronous Signal Processor for Energy Efficient Sensor Nodes.

[BibT_eX]

[DOI]

Jared Tessier

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

A Lightweight Collaborative Fault Tolerant Target Localization System for Wireless Sensor Networks.

[BibT_eX]

[DOI]

IEEE Trans. Mob. Comput., 2009

Fast Variable Padding Motion Estimation Using Smart Zero Motion Prejudgment Technique for Pixel and Frequency Domains.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2009

The land of pixels hosts ICIP 2009 [Conference Spotlight].

[BibT_eX]

[DOI]

IEEE Signal Process. Mag., 2009

Smart-flooding: A novel scheme for fault-tolerant NoCs.

[BibT_eX]

[DOI]

Azeez Sanusi

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

EB-MAC: An Event Based Medium Access Control for Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the Seventh Annual IEEE International Conference on Pervasive Computing and Communications, 2009

Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A Low Complexity Inter Mode Decision for MPEG-2 to H.264/AVC Video Transcoding in Mobile Environments.

[BibT_eX]

[DOI]

Mohsen Shaaban

Proceedings of the 11th IEEE International Symposium on Multimedia, 2009

A Hybrid Adaptive Scheme based on Selective Gaussian Modeling for Real-time Object Detection.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Enhanced Efficient Diamond Search Algorithm for Fast Block Motion Estimation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Data Fusion Framework for Sand Detection in Pipelines.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Robust object tracking using correspondence voting for smart surveillance visual sensing nodes.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2009

"Voodoo" error prediction for bit-depth scalable video coding.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2009

An efficient adaptive manipulation architecture for real time video coding in Frequency Domain.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2009

A multi-modal automatic image registration technique based on complex wavelets.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2009

2008

Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Transition Skew Coding for Global On-Chip Interconnect.

[BibT_eX]

[DOI]

Miriam J. Akl

IEEE Trans. Very Large Scale Integr. Syst., 2008

Single-Phase SP-Domino: A Limited-Switching Dynamic Circuit Technique for Low-Power Wide Fan-in Logic Gates.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Self-Sleep Buffer for Distributed MTCMOS Design.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Guaranteeing QoS with the pipelined multi-channel central caching NoC communication architecture.

[BibT_eX]

[DOI]

Azeez Sanusi

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

High speed single-ended pseudo differential current sense amplifier for SRAM cell.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A generalized fast motion estimation algorithm using external and internal stop search techniques for H.264 video coding standard.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Cost-effective and low-power memory address bus encodings.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An efficient frequency domain intra prediction for H.264/AVC.

[BibT_eX]

[DOI]

Mohsen Shaaban

Proceedings of the International Conference on Image Processing, 2008

Power analysis of the Huffman decoding tree.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2008

A gradient-based hybrid image fusion scheme using object extraction.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2008

Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Low-Power Cache Design Using 7T SRAM Cell.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Novel Adaptive Body Biasing Techniques for Energy Efficient Subthreshold CMOS Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2007

A network of sensor-based framework for automated visual surveillance.

[BibT_eX]

[DOI]

J. Netw. Comput. Appl., 2007

A framework for assessing residual energy in wireless sensor network.

[BibT_eX]

[DOI]

Mitun Bhattacharyya

Int. J. Sens. Networks, 2007

System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

Hybrid multiplierless FIR filter architecture based on NEDA.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2007, 2007

PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Adaptive Techniques for a Fast Frequency Domain Motion Estimation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Fully Decentralized Weighted Kalman Filter for Wireless Sensor Networks with FuzzyART Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Symposium on Computers and Communications (ISCC 2007), 2007

A Low Power Domino with Differential-Controlled-Keeper.

[BibT_eX]

[DOI]

Weidong Kuang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low Power 4-bit Interleaved Burst Sampling ADC for Sub-GHz Impulse UWB Radio.

[BibT_eX]

[DOI]

Xiaodong Zhang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An Adaptive Block Size Phase Correlation Motion Estimation Using Adaptive Early Search Termination Technique.

[BibT_eX]

[DOI]

Mohsen Shaaban

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design and Realization of Analog Phi-Function for LDPC Decoder.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Pixel-Level Image Fusion Scheme based on Linear Algebra.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing Applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Low Power Lookup Tables for Huffman Decoding.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2007

New Wireless Sensors Networks: The Art of Integration.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Intelligent Mechanisms for Energy Reduction in Design of Wireless Sensor Networks using Learning Methods.

[BibT_eX]

[DOI]

Mitun Bhattacharyya

Proceedings of the Integrated Intelligent Systems for Engineering Design, 2006

A New Efficient Block-Matching Algorithm for Motion Estimation.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

Editorial.

[BibT_eX]

[DOI]

Samia A. Mashali

J. VLSI Signal Process., 2006

High-Speed and Low-Power IP for Embedded Block Coding with Optimized Truncation (EBCOT) Sub-Block in JPEG2000 System Implementation.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

MAC-SCC: a medium access control protocol with separate control channel for reconfigurable multi-hop wireless networks.

[BibT_eX]

[DOI]

IEEE Trans. Wirel. Commun., 2006

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

NEDA: a low-power high-performance DCT architecture.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2006

A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2006

Design methodologies for high-performance noise-tolerant XOR-XNOR circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

An Efficient Data Reuse Motion Estimation Engine.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

A low power adaptive transmitter architecture for low band UWB applications.

[BibT_eX]

[DOI]

Xiaodong Zhang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A power-efficient architecture for EBCOT tier-1 in JPEG 2000.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A low-power clock frequency multiplier.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Multi-Path Search Algorithm for Block-Based Motion Estimation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2006

Area-Efficient NEDA Architecture for The 1-D DCT/IDCT.

[BibT_eX]

[DOI]

Archana Chidanandan

Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

2005

Coefficient Elimination Algorithm for Low Energy Distributed Arithmetic DCT Architectures.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2005

Efficient shield insertion for inductive noise reduction in nanometer technologies.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

A Fast Scheduling Algorithm for Low Power Design.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2005

Noise Metrics in Flip-Flop Designs.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

Autonomous Decentralized Systems Based Approach to Object Detection in Sensor Clusters.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2005

Editorial.

[BibT_eX]

[DOI]

Bertrand Y. Zavidovique

EURASIP J. Adv. Signal Process., 2005

Dynamic fraction control bus: new SOC on-chip communication architecture design.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Novel 7T sram cell for low power cache design.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Precharged SRAM cell for ultra low-power on-chip cache.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Wireless Sensor Networks: A New Life Paradigm.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic.

[BibT_eX]

[DOI]

Soujanya Venigalla

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A partial parallel algorithm and architecture for arithmetic encoder in JPEG2000.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low complexity decimation filter for multi-standard digital receivers.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A systematic framework for high throughput MAP decoder VLSI architectures.

[BibT_eX]

[DOI]

Mahmoud Elassal

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Novel systolic array architecture for the decorrelator using conjugate gradient for least squares algorithm.

[BibT_eX]

[DOI]

Archana Chidanandan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Dual sense amplified bit lines (DSABL) architecture for low-power SRAM design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Three-level parallel high speed architecture for EBCOT in JPEG2000.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Novel high-throughput EBCOT architecture for JPEG2000.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Noise-tolerant high fan-in dynamic CMOS circuit design.

[BibT_eX]

[DOI]

Pradeep Golconda

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Fraction Control Bus: A New SoC On-chip Communication Architecture Design.

[BibT_eX]

Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

An Architecture for Automated Scene Understanding.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 2005

2004

A Low Power Architecture for HASM Motion Tracking.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2004

High-performance and low-power conditional discharge flip-flop.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Low Power Full Search Block Matching Motion Estimation Vlsi Architectures.

[BibT_eX]

[DOI]

Bertrand Y. Zavidovique

J. Circuits Syst. Comput., 2004

A methodology for low power scheduling with resources operating at multiple voltages.

[BibT_eX]

[DOI]

Integr., 2004

A Double-Edge Implicit-Pulsed Level Convert Flip-Flop.

[BibT_eX]

[DOI]

C. Archana

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

New Bulk Dynamic Threshold NMOS Schemes for Low-Energy Subthreshold Domino-Like Circui.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Contention reduced/conditional discharge flip-flops for level conversion in CVS systems.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Power efficient architecture for (3, 6)-regular low-density parity-check code decoder.

[BibT_eX]

Mahmoud Elassal

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

B-DTNMOS: a novel bulk dynamic threshold NMOS scheme.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Enhanced Parallel Interference Cancellation using Decorrelator for the base-station receiver.

[BibT_eX]

Archana Chidanandan

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Hopfield associative memory on mesh.

[BibT_eX]

Haissam Ziade

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A data merging technique for high-speed low-power multiply accumulate units.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Dynamic profiling algorithms for low bit rate video applications.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003

Discrete Wavelet Transform: Architectures, Design and Performance Issues.

[BibT_eX]

[DOI]

Michael Weeks

J. VLSI Signal Process., 2003

Efficient Mapping Algorithm of Multilayer Neural Network on Torus Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2003

A computational kernel for fast and efficient compressed-domain calculations of wavelet subband energies.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Low power very large scale integration prototype for three-dimensional discrete wavelet transform processor with medical applications.

[BibT_eX]

[DOI]

J. Electronic Imaging, 2003

Editorial.

[BibT_eX]

[DOI]

Shuvra S. Bhattacharyya

Rudy Lauwereins

EURASIP J. Adv. Signal Process., 2003

Energy Efficient and Noise-Tolerant XOR-XNOR Circuit Design.

[BibT_eX]

Proceedings of the International Conference on VLSI, 2003

Novel Design Methodology for High-Performance XOR-XNOR Circuit Design.

[BibT_eX]

[DOI]

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction.

[BibT_eX]

[DOI]

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

A Novel Technique for Noise-Tolerance in Dynamic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies.

[BibT_eX]

[DOI]

Kannan S. Tharmalingam

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Digital IF decimation filters for 3G systems using pipeline/interleaving architecture.

[BibT_eX]

[DOI]

Bertrand Y. Zavidovique

Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003

Noise-constrained interconnect optimization for nanometer technologies.

[BibT_eX]

[DOI]

Kannan S. Tharmalingam

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Memory accesses reduction for MIME algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

An efficient minimum area spacing algorithm for noise reduction.

[BibT_eX]

[DOI]

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

MAC-SCC: Medium Access Control with a Separate Control Channel for Multihop Wireless Networks.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Distributed Computing Systems Workshops (ICDCS 2003 Workshops), 2003

Parallel high-speed architecture for EBCOT in JPEG2000.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

Noise tolerant low voltage XOR-XNOR for fast arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Fault Tolerant Hopfield Associative Memory on Torus.

[BibT_eX]

[DOI]

Haissam Ziade

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Low Power Conditional-Discharge Pulsed Flip-Flops.

[BibT_eX]

Proceedings of the International Conference on Embedded Systems and Applications, 2003

2002

A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2002

Performance analysis of low-power 1-bit CMOS full adder cells.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Three-dimensional discrete wavelet transform architectures.

[BibT_eX]

[DOI]

Michael Weeks

IEEE Trans. Signal Process., 2002

Algorithm-based low-power VLSI architecture for 2D mesh video-object motion tracking.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2002

A Low Power High Performance Distributed DCT Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Noise-tolerant design and analysis for a low-voltage dynamic full adder cell.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Low power SOVA architecture using bi-directional scheme.

[BibT_eX]

[DOI]

Mahmoud Elassal

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

On low power high level synthesis using genetic algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A merged multiplier-accumulator for high speed signal processing applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2002

Low power full search block matching motion estimation architecture.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Digital and Computational Video, 2002

A low power VLSI architecture for multistage interval-based motion estimation (MIME) algorithm.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Digital and Computational Video, 2002

Systolic array architectures for full-search block matching motion estimation.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Digital and Computational Video, 2002

2001

Efficient low-bit-rate adaptive mesh-based motion compensation technique.

[BibT_eX]

[DOI]

Proceedings of the Visual Information Processing X, Orlando, FL, USA, April 16, 2001, 2001

A low power 10-transistor full adder cell for embedded architectures.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Enhanced low power motion estimation VLSI architectures for video compression.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A mesh based motion tracking architecture.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Hybrid Mesh-Based/Block-Based Motion Compensation Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Workshop on Digital and Computational Video (DCV 2001), 2001

2000

Video codec incorporating block-based multihypothesis motion-compensated prediction.

[BibT_eX]

Proceedings of the Visual Communications and Image Processing 2000, 2000

Low-bit-rate generalized quad-tree motion compensation algorithm and its optimal encoding schemes.

[BibT_eX]

Proceedings of the Visual Communications and Image Processing 2000, 2000

A high-performance 1D-DCT architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A VLSI architecture for hierarchical mesh based motion compensation using scalable affine transformation core.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A New Block-Matching Motion Estimation Algorithm Based on Successive Elimination.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Conference on Image Processing, 2000

An efficient low-bit rate adaptive mesh-based motion compensation technique.

[BibT_eX]

[DOI]

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

A scalable affine core for mesh-based video object motion compensation.

[BibT_eX]

[DOI]

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

On minimizing hierarchical mesh coding overhead: (HASM) hierarchical adaptive structured mesh approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2000

Compressed Domain Texture Classification from a Modified EZW Symbol Stream.

[BibT_eX]

[DOI]

Proceedings of the Data Compression Conference, 2000

An Efficient Successive Elimination Algorithm for Block-Matching Motion Estimation.

[BibT_eX]

[DOI]

Proceedings of the Data Compression Conference, 2000

An Efficient Low-Bit Rate Motion Compensation Technique Based on Quadtree.

[BibT_eX]

[DOI]

Proceedings of the Data Compression Conference, 2000

Compressed-Domain Classification of Texture Images.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000

A Scalable Affine Core for Video Object Motion Compensation.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000

A 108 Gbps, 1.5 GHz 1D-DCT Architecture.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

A Multiplication-Free Parallel Architecture for Affine Transformation.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999

Performance analysis for a new automatic error control system for overcoming atmospheric multipath fading with random bit errors for wireless ATM networks.

[BibT_eX]

[DOI]

M. Mazen Al-Khatib

Proceedings of the 1999 IEEE Wireless Communications and Networking Conference, 1999

Performance Analysis for a New Automatic Error Control System for Overcoming Turbulent Fading Errors for Wireless ATM Networks.

[BibT_eX]

[DOI]

M. Mazen Al-Khatib

Proceedings of the Fourth IEEE Symposium on Computers and Communications (ISCC 1999), 1999

A low power prototype for a 3D discrete wavelet transform processor.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Performance evaluation of 1-bit CMOS adder cells.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A 10-transistor low-power high-speed full adder cell.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A non-zero clock skew scheduling algorithm for high speed clock distribution network.

[BibT_eX]

[DOI]

M. B. Maaz

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Minimizing switchings of the function units through binding for low power.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Multiple voltage-based scheduling methodology for low power in the high level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Methodologies for binding function units for low power in high level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A low power and high performance core for planar object overlaying.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design, 1999

1998

A Vlsi Architecture for Separable 2-D Discrete Wavelet Transform.

[BibT_eX]

[DOI]

Jimmy C. Limqueco

J. VLSI Signal Process., 1998

Three-dimensional defect sensitivity modeling for open circuits in ULSI structures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

A New Full Adder Cell for Low-Power Applications.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997

An Efficient Mapping Algorithm of Multilayer Perceptron on Mesh-connected Architectures.

[BibT_eX]

[DOI]

Parallel Algorithms Appl., 1997

T1: Multimedia.

[BibT_eX]

[DOI]

K. R. Rao

T. V. Subramaniam

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A prototype chipset for a large scaleable ATM switching node.

[BibT_eX]

[DOI]

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

A low power based system partitioning and binding technique for multi-chip module architectures.

[BibT_eX]

[DOI]

H. Krishnamurthy

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1996

Correction to "Efficient Mapping of ANNs on Hypercube Massively Parallel Machines".

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

The Extended Cube Connected Cycles: An Efficient Interconnection for Massively Parallel Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

A Graph-Based Approach to the Synthesis of Multi-Chip Module Architectures.

[BibT_eX]

[DOI]

Jijun Chen

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A new ATM switch architecture: scalable shared buffer.

[BibT_eX]

[DOI]

D. Seidel

A. Raju

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

A High Speed VLSI Architecture for Scaleable ATM Switches.

[BibT_eX]

[DOI]

Paul Shipley

Sherif Sayed

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

Tree-based special-purpose Array architectures for neural computing.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1995

Introduction.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1995

Efficient Mapping of ANNs on Hypercube Massively Parallel Machines.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1995

A New Thinning Algorithm for Arabic Character Using Self-Organizing Neural Network.

[BibT_eX]

[DOI]

Majid M. Altowairjri

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A new ATM congestion control scheme for shared buffer switch architectures.

[BibT_eX]

[DOI]

Aditya Agrawal

Amr Elchouemi

Proceedings of the 4th International Conference on Computer Communications and Networks (ICCCN '95), 1995

A scalable analog architecture for neural networks with on-chip learning and refreshing.

[BibT_eX]

[DOI]

Bassem A. Alhalabi

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

A scalable shared buffer ATM switch architecture.

[BibT_eX]

[DOI]

Aditya Agrawal

Anand Raju

Sachidanand Varadarajan

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994

The Hierarchical Hypercube: A New Interconnection Topology for Massively Parallel Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1994

Bitonic Sort on the Connection Machine.

[BibT_eX]

[DOI]

Parallel Algorithms Appl., 1994

Parameterized Modeling of Open-Circuit Critical Volume for Three-Dimensional Defects in VLSI Processing.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on VLSI Design, 1994

Storage Allocation Strategies for Data Path Synthesis of ACICs.

[BibT_eX]

[DOI]

N. A. Ramakrishna

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Arabic Text Recognition Using Neural Networks.

[BibT_eX]

[DOI]

Majid M. Altuwaijri

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Automated system partitioning for synthesis of multi-chip modules.

[BibT_eX]

[DOI]

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993

An Efficient Mapping of Multilayer Perceptron with Backpropagation ANNs on Hypercubes.

[BibT_eX]

[DOI]

Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

Parallel Implementation of a Cut and Paste Maze Routing Algorithm.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

On the Hierarchical Hypercube Interconnection Network.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Parallel Processing Symposium, 1993

An application-specific array architecture for feedforward with backpropagation ANNs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Application-Specific Array Processors, 1993

1992

VLSI parallel architecture for Kalman filterAn algorithm specific approach.

[BibT_eX]

[DOI]

Padma Rao

Bassem A. Alhalabi

J. VLSI Signal Process., 1992

Image segmentation on a 2D array by a directed split and merge procedure.

[BibT_eX]

[DOI]

Akhilesh Tyagi

IEEE Trans. Signal Process., 1992

A Reconfiguration Technique for Reliable VLSI DSP Array Processors.

[BibT_eX]

[DOI]

Sanjay P. Popli

Akash Tyagi

J. Circuits Syst. Comput., 1992

Properties and Performance of the Hierarchical Hypercube.

[BibT_eX]

[DOI]

Proceedings of the 6th International Parallel Processing Symposium, 1992

SDS: a framework for the design of DSP ASICs.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

1991

VLSI implementation of a systolic database machine for relational algebra and hashing.

[BibT_eX]

[DOI]

Lois M. L. Delcambre

Integr., 1991

A Parallelized Algorithm for the All-Row Preconditioned Interval Newton/Generalized Bisection Method.

[BibT_eX]

Proceedings of the Fifth SIAM Conference on Parallel Processing for Scientific Computing, 1991

From Algorithms to Parallel Architectures: A Formal Approach.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

A high speed pipelined FFT processor.

[BibT_eX]

[DOI]

Proceedings of the 1991 International Conference on Acoustics, 1991

1990

Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Systolic array implementation of image segmentation by a directed split and merge procedure.

[BibT_eX]

[DOI]

Aakash Tyagi

Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

Formal Synthesis of a Parallel Architectures from Recursive Equations.

[BibT_eX]

Proceedings of the 1990 International Conference on Parallel Processing, 1990

A formal high level synthesis approach for DSP architectures.

[BibT_eX]

[DOI]

Proceedings of the 1990 International Conference on Acoustics, 1990

A formal design methodology for parallel architectures.

[BibT_eX]

[DOI]

Proceedings of the Application Specific Array Processors, 1990

A Framework for High Level Synthesis of Digital Architectures from U-Recursive Algorithms.

[BibT_eX]

[DOI]

Proceedings of the ACM 18th Annual Computer Science Conference on Cooperation, 1990

1989

Systematic Algorithm Mapping for Multidimensional Systolic Arrays.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 1989

The design and implementation of multidimensional systolic arrays for DSP applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1989

θ(logN) architectures for RNS arithmetic decoding.

[BibT_eX]

[DOI]

K. P. Lee

Proceedings of the 9th Symposium on Computer Arithmetic, 1989

1988

Algorithms for High Speed Multi-Dimensional Arithmetic and DSP Systolic Arrays.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1988

A fault-tolerant bit-serial array structure for digital filters.

[BibT_eX]

[DOI]

Rajat Roy

Proceedings of the IEEE International Conference on Acoustics, 1988

Multi-dimensional systolic networks for DSP algorithms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1988

Reliable modulo systolic arrays for DSP algorithms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1988

1987

A quadratic residue processor for complex DSP applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1987

1986

Lower bounds for VLSI implementation of residue number system architectures.

[BibT_eX]

[DOI]

Integr., 1986

A VLSI array for computing the DFT based on RNS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1986

1985

Vlsi Implementaton of residue number System Architectures.

[BibT_eX]

[DOI]

PhD thesis, 1985

An efficient VLSI adder for DSP architectures based on RNS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1985

A VLSI implementation of an FFT/NTT computational unit.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1985

1984

A VLSI model for residue number system architectures.

[BibT_eX]

[DOI]

Integr., 1984

A systolic (VLSI) array using RNS for digital signal processing applications.

[BibT_eX]

[DOI]

Proceedings of the ACM 12th annual computer science conference on SIGCSE symposium, 1984

1983

An area-time efficient NMOS adder.

[BibT_eX]

[DOI]

Integr., 1983

Models for VLSI implementation of residue number system arithmetic modules.

[BibT_eX]

[DOI]