Rahul Kundu

According to our database, Rahul Kundu authored at least 9 papers between 1999 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A Distributed Error and Anomaly Communication Architecture for Analog and Mixed-Signal Systems.

Rahul Kundu, Fei Su, Prashant Goteti

J. Electron. Test., 2019

2008

CONCAT: CONflict Driven Learning in ATPG for Industrial designs.

Surendra Bommu, Kameshwar Chandrasekar, Rahul Kundu, Sanjay Sengupta

Proceedings of the 2008 IEEE International Test Conference, 2008

2003

Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk.

Rahul Kundu, R. D. (Shawn) Blanton

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

ATPG for Noise-Induced Switch Failures in Domino Logic.

Rahul Kundu, R. D. (Shawn) Blanton

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

Test vector generation for charge sharing failures in dynamic logic.

Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits.

Rahul Kundu, R. D. (Shawn) Blanton

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

2001

Testing of Dynamic Logic Circuits Based on Charge Sharing.

Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000

Identification of crosstalk switch failures in domino CMOS circuits.

Rahul Kundu, Ronald D. Blanton

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999

A Systematic DFT Procedure for Library Cells.

Jingjing Xu, Rahul Kundu, F. Joel Ferguson

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999