Keerthi Heragu

According to our database, Keerthi Heragu authored at least 16 papers between 1994 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques.

Gordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao, Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2005

A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels.

Robert Payne, Paul E. Landman, Bhavesh Bhakta, Sridhar Ramaswamy, Song Wu, John D. Powers, M. Ulvi Erdogan, Ah-Lyan Yee, Richard Gu, Lin Wu, Yiqun Xie, Bharadwaj Parthasarathy, Keith C. Brouse, Wahed Mohammed, Keerthi Heragu, Vikas Gupta, Lisa Dyson, Wai Lee

IEEE J. Solid State Circuits, 2005

2002

Test vector generation for charge sharing failures in dynamic logic.

Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001

Testing of Dynamic Logic Circuits Based on Charge Sharing.

Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

1999

A Test Generator for Segment Delay Faults.

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998

New Techniques to Verify Timing Correctness of Integrated Circuits

Keerthi Heragu

PhD thesis, 1998

Where We Might Stumble with Embedded-System Test.

Keerthi Heragu

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997

Improving a nonenumerative method to estimate path delay fault coverage.

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Fast identification of untestable delay faults using implications.

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

Segment delay faults: a new fault model.

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Improving accuracy in path delay fault coverage estimation.

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

SIGMA: a simulator for segment delay faults.

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

Fault coverage estimation by test vector sampling.

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Statistical methods for delay fault coverage analysis.

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1994

FACTS: fault coverage estimation by test vector sampling.

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

An Efficient Path Delay Fault Coverage Estimator.

Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the 31st Conference on Design Automation, 1994