Sanjay Sengupta

According to our database, Sanjay Sengupta authored at least 8 papers between 1998 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2014

A Cube-Aware Compaction Method for Scan ATPG.

Sharada Jha, Kameshwar Chandrasekar, Weixin Wu, Ramesh Sharma, Sanjay Sengupta, Sudhakar M. Reddy

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2012

A scan pattern debugger for partial scan industrial designs.

Kameshwar Chandrasekar, Supratik K. Misra, Sanjay Sengupta, Michael S. Hsiao

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Low Coverage Analysis using dynamic un-testability debug in ATPG.

Kameshwar Chandrasekar, Surendra Bommu, Sanjay Sengupta

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2008

CONCAT: CONflict Driven Learning in ATPG for Industrial designs.

Surendra Bommu, Kameshwar Chandrasekar, Rahul Kundu, Sanjay Sengupta

Proceedings of the 2008 IEEE International Test Conference, 2008

2004

Test Strategies for Nanometer Technologies.

Sanjay Sengupta

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2001

Test Challenges in Nanometer Technologies.

Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche

J. Electron. Test., 2001

2000

Test challenges in nanometer technologies.

Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche

Proceedings of the 5th European Test Workshop, 2000

1998

Impact and Cost of Modeling Memories for ATPG for Partial Scan Designs.

Sitaram Yadavalli, Sanjay Sengupta

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998