F. Joel Ferguson

According to our database1, F. Joel Ferguson authored at least 43 papers between 1983 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2007
On state reduction of incompletely specified finite state machines.
Comput. Electr. Eng., 2007

2006
Test sequence generation for controller verification and test with high coverage.
ACM Trans. Design Autom. Electr. Syst., 2006

2005
Detection probabilities of interconnect breaks: an analysis.
Integr., 2005

2004
Estimating detection probability of interconnect opens using stuck-at tests.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2002
Testing Finite State Machines Based on a Structural Coverage Metric .
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines.
Proceedings of the 2002 Design, 2002

1999
A Systematic DFT Procedure for Library Cells.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Checking sequence generation for asynchronous sequential elements.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
Diagnosing realistic bridging faults with single stuck-at information.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On applying non-classical defect models to automated diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Cache RAM inductive fault analysis with fab defect modeling.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
A methodolgy for characterizing cell testability.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Incorporating Physical Design-for-Test into Routing.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Bridging Fault Diagnosis in the Absence of Physical Information.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
Charge-based fault simulation for CMOS network breaks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Detection of Multiple Faults in Two-Dimensional ILAs.
IEEE Trans. Computers, 1996

An unexpected factor in testing for CMOS opens: the die surface.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Maximum Likelihood Estimation for Yield Analysis.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
Diagnosis of realistic bridging faults with single stuck-at information.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Eliminating undetectable shorts between horizontal wires during channel routing.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Defect Classes - An Overdue Paradigm for CMOS IC.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Testing CMOS Logic Gates for Realistic Shorts.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Carafe: an inductive fault analysis tool for CMOS VLSI circuits.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Physical design for testability for bridges in CMOS circuits.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

1992
On the effectiveness of simultaneous self-test techniques.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991
Test pattern generation for current testable faults in static CMOS circuits.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Test Pattern Generation for Realistic Bridge Faults in CMOS ICs.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990
Detection of multiple faults in MOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Testing for parametric faults in static CMOS circuits.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989
Microprocessor Interfacing and the 68000: Peripherals and systems: Clements, A Wiley and Sons Ltd, Chichester, UK (1989) £39.95 pp 446.
Microprocess. Microsystems, 1989

1988
A CMOS fault extractor for inductive fault analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Book Review: Logic Design Principles by Edward J. McCluskey: Prentice-Hall Publishers, Englewood Cliffs, New Jersey, 549 pp., $39.95.
SIGARCH Comput. Archit. News, 1988

Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis.
Proceedings of the Proceedings International Test Conference 1988, 1988

1985
Inductive Fault Analysis of MOS Integrated Circuits.
IEEE Des. Test, 1985

1984
The Design of Easily Tastabel VLSI Array Multipliers.
IEEE Trans. Computers, 1984

Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells.
Proceedings of the Proceedings International Test Conference 1984, 1984

1983
The design of two easily-testable VLSI array multipliers.
Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983


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