Rainer G. Spallek

Affiliations:
  • Dresden University of Technology, Germany


According to our database1, Rainer G. Spallek authored at least 59 papers between 1997 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Possibilities and Challenges for Reconfigurable Hardware and Cloud Architectures in Data-Intensive Scientific Applications.
Proceedings of the 2020 Seventh International Conference on Software Defined Systems, 2020

Real-Time Data Compression System for Data-Intensive Scientific Applications Using FPGA Architecture.
Proceedings of the Applied Informatics and Cybernetics in Intelligent Systems, 2020

2019
Research and implementation of efficient parallel processing of big data at TELBE user facility.
Proceedings of the 2019 Summer Simulation Conference, 2019

2017
Modellierung anwendungsspezifischer Hardware und deren Einbettung in die DBT-basierte Prozessor-Verhaltenssimulation.
Proceedings of the 47. Jahrestagung der Gesellschaft für Informatik, 2017

First Workshop on Hardware Defined Programming - HDP.
Proceedings of the 47. Jahrestagung der Gesellschaft für Informatik, 2017

A New Level of Trusted Cloud Computing - Virtualized Reconfigurable Resources in a Security-First Architecture.
Proceedings of the 47. Jahrestagung der Gesellschaft für Informatik, 2017

2016
Migration of long-running Tasks between Reconfigurable Resources using Virtualization.
SIGARCH Comput. Archit. News, 2016

The portable open-source IP core and utility library PoC.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

RC3E: Reconfigurable Accelerators in Data Centres and Their Provision by Adapted Service Models.
Proceedings of the 9th IEEE International Conference on Cloud Computing, 2016

2015
RC3E: Provision and Management of Reconfigurable Hardware Accelerators in a Cloud Environment.
CoRR, 2015

Kompression von Tracedaten auf Bitebene basierend auf einem LZ77-Wörterbuchansatz.
Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik, Energie und Umwelt, INFORMATIK 2015, Cottbus, Germany, September 28, 2015

Computing Framework for Dynamic Integration of Reconfigurable Resources in a Cloud.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
PoC-align: An open-source alignment accelerator using FPGAs.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Ready PCIe data streaming solutions for FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Educating hardware design - From primary school children to postgraduate engineers.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
Superblock compilation and other optimization techniques for a Java-based DPT machine emulator.
Proceedings of the ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (co-located with ASPLOS 2013), 2013

Integration of a Highly Scalable, Multi-FPGA-Based Hardware Accelerator in Common Cluster Infrastructures.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

Weasel: A platform-independent streaming-optimized SATA controller.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Integration of a multi-FPGA system in a common cluster environment.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Increasing the efficiency of an embedded multi-core bytecode processor using an object cache.
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems, 2012

Comparison of Trace-Port-Designs for On-Chip-Instruction-Trace.
Proceedings of the 3th IEEE Germany Student Conference, 2012

Short-Read Mapping by a Systolic Custom FPGA Computation.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
The Java Virtual Machine in retargetable, high-performance instruction set simulation.
Proceedings of the 9th International Conference on Principles and Practice of Programming in Java, 2011

Next-generation massively parallel short-read mapping on FPGAs.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

Accelerating Computations on FPGA Carry Chains by Operand Compaction.
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

2010
Application requirements and efficiency of embedded Java bytecode multi-cores.
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems, 2010

Solving Sudokus through an incidence matrix on an FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

An Embedded GC Module with Support for Multiple Mutators and Weak References.
Proceedings of the Architecture of Computing Systems, 2010

2009
High-Level Architecture Modelling Assisting the Processor Platform Development, Debugging and Simulation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

Mapping basic prefix computations to fast carry-chain structures.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Generating the trace qualification configuration for MCDS from a high level language.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Java-Programmed Bootloading in Spite of Load-Time Code Patching on a Minimal Embedded Bytecode Processor.
Proceedings of the 2008 International Conference on Embedded Systems & Applications, 2008

Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Bump-pointer method caching for embedded Java processors.
Proceedings of the 5th International Workshop on Java Technologies for Real-time and Embedded Systems, 2007

Enabling constant-time interface method dispatch in embedded Java processors.
Proceedings of the 5th International Workshop on Java Technologies for Real-time and Embedded Systems, 2007

Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Implementation of Architecture Concepts for Hardware Agent Systems.
Proceedings of the Seventh International Conference on Computer and Information Technology (CIT 2007), 2007

2006
Analysis of a Fully-Scalable Digital Fractional Clock Divider.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Prototyping and Application Development Framework for Dynamically Reconfigurable DSP Architectures.
Proceedings of the ARCS 2006, 2006

A Compiler-Oriented Architecture Description for Reconfigurable Systems.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Design space exploration of coarse-grain reconfigurable DSPs.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

Ein Zwischenformat-Profiler für das RECAST-Framework.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

2004
Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration.
Proceedings of the Field Programmable Logic and Application, 2004

RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded Computing.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures.
Proceedings of the Organic and Pervasive Computing, 2004

2003
Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Improving Code Efficiency for Reconfigurable VLIW Processors.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Prototyping Framework for Reconfigurable Processors.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
Experimenteller Vergleich verschiedener Entwurfsmethoden für FPGA-basierte Entwurfsabläufe.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

Formal Verification of a Reconfigurable Microprocessor.
Proceedings of the Field-Programmable Logic and Applications, 2000

Formal Verification for Microprocessors with Extendable Instruction Set.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999
Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic.
Proceedings of the Parallel and Distributed Processing, 1999

A Concept for an Evaluation Framework for Reconfigurable Systems.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

1998
Common Logging Interface - Ein System zum Sammeln und Verarbeiten von Debugnachrichten in verteilten Umgebungen.
Proceedings of the JIT '98, 1998

Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays.
Proceedings of the Field-Programmable Logic and Applications, 1998

1997
Bewertung von modernen Rechnerarchitekturen hinsichtlich numerischer Simulationen auf heterogenen Plattformen.
Proceedings of the MMB '97, 1997

A RISC Processor with Extended Forwarding.
Proceedings of the Architektur von Rechensystemen, Arbeitsteilige Systemarchitekturen: Konzepte, Lösungen, Anwendungen, Trends, 1997


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