Rajat Aggarwal

According to our database1, Rajat Aggarwal authored at least 17 papers between 1997 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
SABER: A Scalable Action-Based Embodied Dataset for Real-World VLA Adaptation.
CoRR, May, 2026

PRISM: A Multi-View Multi-Capability Retail Video Dataset for Embodied Vision-Language Models.
CoRR, March, 2026

2017
Clock-Aware FPGA Placement Contest.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

2016
Routability-Driven FPGA Placement Contest.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

An Interactive Physical Synthesis Methodology for High-Frequency FPGA Designs.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

Detection and segmentation of mirror-like surfaces using structured illumination.
Proceedings of the Tenth Indian Conference on Computer Vision, 2016

Visualizing Malaria Spread Under Climate Variability.
Proceedings of the 4th Workshop on Visualisation in Environmental Sciences, 2016

Panoramic Stereo Videos with a Single Camera.
Proceedings of the 2016 IEEE Conference on Computer Vision and Pattern Recognition, 2016

2015
Online handwriting recognition using depth sensors.
Proceedings of the 13th International Conference on Document Analysis and Recognition, 2015

2014
FPGA place & route challenges.
Proceedings of the International Symposium on Physical Design, 2014

2009
Solving modern mixed-size placement instances.
Integr., 2009

2008
Architecture-specific packing for virtex-5 FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2006
Solving hard instances of floorplacement.
Proceedings of the 2006 International Symposium on Physical Design, 2006

A Novel Earthquake Mitigation Information expert System: EMIS.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

1999
Multilevel hypergraph partitioning: applications in VLSI domain.
IEEE Trans. Very Large Scale Integr. Syst., 1999

1997
Speeding up technology-independent timing optimization by network partitioning.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Multilevel Hypergraph Partitioning: Application in VLSI Domain.
Proceedings of the 34st Conference on Design Automation, 1997


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